SST25VF016B-75-4I-S2AF Microchip Technology, SST25VF016B-75-4I-S2AF Datasheet - Page 5
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SST25VF016B-75-4I-S2AF
Manufacturer Part Number
SST25VF016B-75-4I-S2AF
Description
IC FLASH SER 16M 75MHZ SPI 8SOIC
Manufacturer
Microchip Technology
Specifications of SST25VF016B-75-4I-S2AF
Memory Type
FLASH
Memory Size
16M (2M x 8)
Format - Memory
FLASH
Speed
75MHz
Interface
SPI Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Ic Interface Type
SPI
Clock Frequency
80MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
SOIC
No. Of Pins
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SST25VF016B-75-4I-S2AF
Manufacturer:
SHARP
Quantity:
1 200
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Part Number:
SST25VF016B-75-4I-S2AF
Manufacturer:
SST/44
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5 288
Company:
Part Number:
SST25VF016B-75-4I-S2AF
Manufacturer:
MICROCHIP
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3 504
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SST25VF016B-75-4I-S2AF
Manufacturer:
SST
Quantity:
20 000
Company:
Part Number:
SST25VF016B-75-4I-S2AF-T
Manufacturer:
Microchip Technology
Quantity:
1 650
A Microchip Technology Company
©2011 Silicon Storage Technology, Inc.
Memory Organization
Device Operation
The SST25VF016B SuperFlash memory array is organized in uniform 4 KByte erasable sectors with
32 KByte overlay blocks and 64 KByte overlay erasable blocks.
The SST25VF016B is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol.
The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is
accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).
The SST25VF016B supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is
high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock
signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal.
Figure 3: SPI Protocol
SCK
CE#
SO
SI
MODE 3
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
HIGH IMPEDANCE
5
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
16 Mbit SPI Serial Flash
DON T CARE
SST25VF016B
MODE 3
MODE 0
S71271-04-000
1271 SPIprot.0
Data Sheet
01/11