AT25DF161-SSH-B Atmel, AT25DF161-SSH-B Datasheet - Page 39

IC FLASH 16MBIT 100MHZ 8SOIC

AT25DF161-SSH-B

Manufacturer Part Number
AT25DF161-SSH-B
Description
IC FLASH 16MBIT 100MHZ 8SOIC
Manufacturer
Atmel
Datasheet

Specifications of AT25DF161-SSH-B

Format - Memory
FLASH
Memory Type
DataFLASH
Memory Size
16M (2M x 8)
Speed
100MHz
Interface
SPI, RapidS
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Density
16Mb
Access Time (max)
5ns
Interface Type
Serial (SPI)
Boot Type
Not Required
Address Bus
1b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
SOIC
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
2M
Supply Current
19mA
Mounting
Surface Mount
Pin Count
8
Mounting Style
SMD/SMT
Memory Configuration
8192 Pages X 256 Bytes
Clock Frequency
100MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
SOIC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT25DF161-SSH-B
Manufacturer:
ROHM
Quantity:
40 000
3687E–DFLASH–11/10
12.5
Figure 12-4. Resume from Deep Power-Down
Hold
The HOLD pin is used to pause the serial communication with the device without having to stop or reset the clock
sequence. The Hold mode, however, does not have an affect on any internally self-timed operations such as a program or
erase cycle. Therefore, if an erase cycle is in progress, asserting the HOLD pin will not pause the operation, and the erase
cycle will continue until it is finished.
The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated simply by asserting the HOLD
pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse, then the Hold mode won’t be started
until the beginning of the next SCK low pulse. The device will remain in the Hold mode as long as the HOLD pin and CS pin
are asserted.
While in the Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the SCK pin will be
ignored. The WP pin, however, can still be asserted or deasserted while in the Hold mode.
To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the SCK low pulse. If
the HOLD pin is deasserted during the SCK high pulse, then the Hold mode won’t end until the beginning of the next SCK
low pulse.
If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be
aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state.
SCK
SO
CS
I
SI
CC
Atmel AT25DF161
39

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