EV-ADF4360-9EB1Z Analog Devices, EV-ADF4360-9EB1Z Datasheet - Page 3

• Manufacturer Part Number: EV-ADF4360-9EB1Z
• Description: Clock & Timer Development Tools EVALUATION BOARD
• Manufacturer: Analog Devices
• Type: PLL Synthesizers / Multipliers / Dividersr

Specifications of EV-ADF4360-9EB1Z

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: ADF4360-9
• Frequency: 250 MHz, 400 MHz
• Operating Supply Voltage: 9 V
• Interface Type: USB
• Operating Supply Current: 40 mA
• Factory Pack Quantity: 1

Evaluation Board User Guide
EVALUATION BOARD HARDWARE
The evaluation board comes with a mini-USB cable to connect
to the USB port of a PC. The silkscreen for the evaluation board
is shown in Figure 2. It is important that the software be
installed before connecting the board. If the user encounters
any installation warning messages during connection, select
Continue Anyway. If another Install hardware procedure
wizard runs when the software is executed, allow it to install.
The board schematics are shown in Figure 11, Figure 12, and
Figure 13.
The board is powered from a single 9 V battery or USB connec-
tion. All components necessary for local oscillator (LO) or
DIVOUT generation are available on board. A 19.2 MHz TCXO
from Fox Electronics provides the necessary reference input.
Otherwise, an external reference signal can be connected via J3
(to disable the TCXO, remove R3 and R4). The PLL is composed
of the
from RF
J1, and the complementary output RF
available from J2. DIVOUT is available from J8. Digital lock
detect is present on the SMA marked J6.
ADF4360-9
OUT
A is available through the standard SMA connector,
Figure 2. Evaluation Board Silkscreen—Top View
and a passive loop filter. The VCO output
OUT
B VCO output is
Rev. C | Page 3 of 16
Users can provide their own power supplies using the J4 and J5
connectors, as shown in Figure 2.
The on-board filter is a third-order, passive low-pass filter. It
contains three capacitors (C13, C14, and C15) and two resistors
(R10 and R11). The footprint for R10 is located on the underside
of the board. The design parameters for the loop filter are for a
center frequency of 360 MHz, a PFD frequency of 1600 kHz, and a
low-pass filter bandwidth of 40 kHz. To design a filter for different
frequency setups, use the ADIsimPLL simulation software.
Note that only very high performance measurement equipment
is capable of measuring good jitter performance below 180 MHz.
The Agilent E5052A/E5052B and Rohde & Schwarz FSUP are
both good instruments for this purpose.
RF OUTPUT STAGE
The RF output stage of the board allows the user to insert a
tuned load for a particular frequency. The particular network
inserted in the board is optimized for 360 MHz operation. For
different frequencies, the output stage needs different component
values. Consult the
If in doubt, use a 50 Ω resistor instead of the shunt inductor and
a 100 pF bypass capacitor and 0 Ω resistor instead of the series
inductor.
It is very important that the same components be placed on the
RF
outputs be terminated with 50 Ω loads. Otherwise, the output
power is not optimal, and, in some cases, the part may
malfunction.
In applications that only use the divider, both RF outputs are
best terminated with a shunt 50 Ω resistor to AV
100 pF dc bypass capacitor, and a 50 Ω load to GND.
EXTERNAL INDUCTOR OPTIONS
The
the LC tank circuit of the VCO. The evaluation board has a
footprint for the placement of these. A value of 22 nH is
inserted on the board giving a VCO center frequency of
360 MHz. Insert two 470 Ω resistors (R25 and R26) parallel to
ground for both L1 and L2 (see Figure 3).
OUT
ADF4360-9
A and RF
OUT
uses external inductors (L1 and L2) to set up
ADF4360-9
B lines. In addition, it is essential that both
data sheet for further information.
DD
, a series
UG-106