MAX17050EVKIT# Maxim Integrated, MAX17050EVKIT# Datasheet - Page 25

• Manufacturer Part Number: MAX17050EVKIT#
• Description: Power Management IC Development Tools MAX17050 Eval Kit
• Manufacturer: Maxim Integrated
• Type: Voltage Protectionr
• Series: MAX17047, MAX17050r

Specifications of MAX17050EVKIT#

• Rohs: yes
• Product: Evaluation Kits
• Tool Is For Evaluation Of: MAX17050
• Input Voltage: 2.5 V to 4.5 V
• Interface Type: I2C
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Part # Aliases: 90-BT07K#D00
• For Use With: MAX17050

dV4:dV0—Sets the threshold, which V
against. If the cell’s voltage changes by less than dV over
two consecutive periods set by dt, the cell is considered
relaxed; dV has a range of 0 to 40mV where 1 LSb =
1.25mV. The default value is 1.75mV.
dt3:dt0—Sets the time period over which change in
V
changes by less than dV over two consecutive periods
set by dt, the cell is considered relaxed. The default value
is 6 minutes. The comparison period is calculated as:
Figure 32. Cell Relaxation Detection
Figure 33. LearnCFG Register Format (Input/Output)
Maxim Integrated
CELL
MSb
is compared against dV. If the cell’s voltage
0
CURRENT
AVERAGE
VOLTAGE
Relaxation Period = 2
CELL
0
0
DISCHARGING
1
dt1
MSB—ADDRESS
0
dV2
(RELAXATION BEGINS)
CELL UNLOADED
dt2
0
dt
dV3
dV4
O 0.1758s
CELL
1
dt3
is compared
1
dV5
LSb
0
dt4
ModelGauge m3 Fuel Gauge
dV6
RELAXATION LOAD THRESHOLD
THRESHOLD
READING
MSb
BELOW
FIRST
dv/dt
The LearnCFG register controls all functions relating
to adaptation during operation. The LearnCFG register
default values should not be changed unless specifically
required by the application.
register format:
0—Bit must be written 0. Do not write 1.
1—Bit must be written 1. Do not write 0.
Filt Empty—Empty Detect Filter. This bit selects whether
empty is detected by a filtered or unfiltered voltage read-
ing. Setting this bit to 1 causes the empty detection algo-
rithm to use the AverageV
0 forces the empty detection algorithm to use the V
register. This bit is written to 0 at power-up.
dt5
0
MAX17047/MAX17050
LS
THRESHOLD
2
READING
SECOND
BELOW
dV/dt
dt6
LS
1
LSB—ADDRESS
CELL IS RELAXED
RelDt BIT SET
CELL CAPACITY IS
LEARNED
LS
0
LearnCFG Register (28h)
CELL
0
MINUTES
48 TO 96
Figure 33
register. Setting this bit to
Empty
Filt
LONG RELAXATION
RelDt2 BIT SET
is the LearnCFG
1
LSb
0
CELL
25