IS43R16160B-5TL-TR ISSI, Integrated Silicon Solution Inc, IS43R16160B-5TL-TR Datasheet - Page 4

• Manufacturer Part Number: IS43R16160B-5TL-TR
• Description: IC DDR SDRAM 256MBIT 66TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS43R16160B-5TL-TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOPII
• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 700ps
• Maximum Clock Rate: 200MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS43R83200B
IS43R16160B, IC43R16160B
4
I
DDR SDRAM (Rev.1.1)
PIN FUNCTION
I
UDQS, LDQS (x16)
/RAS, /CAS, /WE
UDM, LDM (x16)
V
DQ0-7 (x8),
DQ0-15 (x16),
CLK, /CLK
V
DM (x8)
DDQ,
DQS (x8)
SYMBOL
DD
BA0,1
A0-12
Vref
CKE
/CS
,
V
V
SSQ
SS
Power Supply
Power Supply
Input / Output
Input / Output
TYPE
Preliminary
Preliminary
Input
Input
Input
Input
Input
Input
Input
Input
V
DESCRIPTION
Clock: CLK and /CLK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK and
negative edge of /CLK. Output (read) data is referenced to the crossings of
CLK and /CLK (both directions of crossing).
Clock Enable: CKE controls internal clock. When CKE is low, internal clock
for the following cycle is ceased. CKE is also used to select auto / self refresh.
After self refresh mode is started, CKE becomes asynchronous input. Self refresh
is maintained as long as CKE is low.
Chip Select: When /CS is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
A0-12 specify the Row / Column Address in conjunction with BA0,1. The
Row Address is specified by A0-12. The Column Address is specified by
A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge
option. When A10 is high at a read / write command, an auto precharge is
performed. When A10 is high at a precharge command, all banks are
precharged.
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
Data Input/Output: Data bus
Data Strobe: Output with read data, input with write data. Edge-aligned
with read data, centered in write data. Used to capture write data.
For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS
correspond to the data on DQ8-DQ15
Input Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7;
UDM corresponds to the data on DQ8-DQ15.
SSTL_2 reference voltage.
Power Supply for the memory array and peripheral circuitry.
DDQ,
and
V
SSQ
are supplied to the Output Buffers only.
256M Double Data Rate Synchronous DRAM
Zentel Electronics Corporation
A3S56D30/40ETP
Integrated Silicon Solution, Inc.
10/31/08
Rev. B