MT47H32M8BP-5E:B TR Micron Technology Inc, MT47H32M8BP-5E:B TR Datasheet - Page 7

• Manufacturer Part Number: MT47H32M8BP-5E:B TR
• Description: IC DDR2 SDRAM 256MBIT 5NS 60FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H32M8BP-5E:B TR

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 256M (32M x 8)
• Speed: 5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

256Mb: x4, x8, x16 DDR2 SDRAM
Figure 51: Bank Read – Without Auto Precharge ............................................................................................. 94
Figure 52: Bank Read – with Auto Precharge ................................................................................................... 95
t
t
Figure 53: x4, x8 Data Output Timing –
DQSQ,
QH, and Data Valid Window .................................................. 96
t
t
Figure 54: x16 Data Output Timing –
DQSQ,
QH, and Data Valid Window ...................................................... 97
t
t
Figure 55: Data Output Timing –
AC and
DQSCK .......................................................................................... 98
Figure 56: Write Burst ................................................................................................................................... 100
Figure 57: Consecutive WRITE-to-WRITE ...................................................................................................... 101
Figure 58: Nonconsecutive WRITE-to-WRITE ................................................................................................ 101
Figure 59: WRITE Interrupted by WRITE ....................................................................................................... 102
Figure 60: WRITE-to-READ ........................................................................................................................... 103
Figure 61: WRITE-to-PRECHARGE ................................................................................................................ 104
Figure 62: Bank Write – Without Auto Precharge ............................................................................................ 105
Figure 63: Bank Write – with Auto Precharge ................................................................................................. 106
Figure 64: WRITE – DM Operation ................................................................................................................ 107
Figure 65: Data Input Timing ........................................................................................................................ 108
Figure 66: Refresh Mode ............................................................................................................................... 109
Figure 67: Self Refresh .................................................................................................................................. 111
Figure 68: Power-Down ................................................................................................................................ 113
Figure 69: READ-to-Power-Down or Self Refresh Entry .................................................................................. 115
Figure 70: READ with Auto Precharge-to-Power-Down or Self Refresh Entry .................................................. 115
Figure 71: WRITE-to-Power-Down or Self Refresh Entry ................................................................................ 116
Figure 72: WRITE with Auto Precharge-to-Power-Down or Self Refresh Entry ................................................. 116
Figure 73: REFRESH Command-to-Power-Down Entry ................................................................................. 117
Figure 74: ACTIVATE Command-to-Power-Down Entry ................................................................................ 117
Figure 75: PRECHARGE Command-to-Power-Down Entry ............................................................................ 118
Figure 76: LOAD MODE Command-to-Power-Down Entry ............................................................................ 118
Figure 77: Input Clock Frequency Change During Precharge Power-Down Mode ........................................... 119
Figure 78: RESET Function ........................................................................................................................... 121
Figure 79: ODT Timing for Entering and Exiting Power-Down Mode .............................................................. 123
Figure 80: Timing for MRS Command to ODT Update Delay .......................................................................... 124
Figure 81: ODT Timing for Active or Fast-Exit Power-Down Mode ................................................................. 124
Figure 82: ODT Timing for Slow-Exit or Precharge Power-Down Modes ......................................................... 125
Figure 83: ODT Turn-Off Timings When Entering Power-Down Mode ............................................................ 125
Figure 84: ODT Turn-On Timing When Entering Power-Down Mode ............................................................. 126
Figure 85: ODT Turn-Off Timing When Exiting Power-Down Mode ............................................................... 127
Figure 86: ODT Turn-On Timing When Exiting Power-Down Mode ................................................................ 128
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256MbDDR2.pdf - Rev. M 7/09 EN
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