IS42S32800D-75ETL-TR ISSI, Integrated Silicon Solution Inc, IS42S32800D-75ETL-TR Datasheet - Page 6

• Manufacturer Part Number: IS42S32800D-75ETL-TR
• Description: IC SDRAM 256MBIT 133MHZ 86TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S32800D-75ETL-TR

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 86-TSOPII
• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 13b
• Access Time (max): 5.5ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 180mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ing this command, the next command for the selected
bank(s) is executed after passage of the period t
IS42S32800D, IS45S32800D
GENERAL DESCRIPTION
READ
The READ command selects the bank from BA0, BA1 inputs
and starts a burst read access to an active row. Inputs
A0-A8 provides the starting column location. When A10 is
HIGH, this command functions as an AUTO PRECHARGE
command. When the auto precharge is selected, the row
being accessed will be precharged at the end of the READ
burst. The row will remain open for subsequent accesses
when AUTO PRECHARGE is not selected. DQ’s read
data is subject to the logic level on the DQM inputs two
clocks earlier. When a given DQM signal was registered
HIGH, the corresponding DQ’s will be High-Z two clocks
later. DQ’s will provide valid data when the DQM signal
was registered LOW.
WRITE
A burst write access to an active row is initiated with the
WRITE command. BA0, BA1 inputs selects the bank,
and the starting column location is provided by inputs
A0-A8. Whether or not AUTO-PRECHARGE is used is
determined by A10.
The row being accessed will be precharged at the end of
the WRITE burst, if AUTO PRECHARGE is selected. If
AUTO PRECHARGE is not selected, the row will remain
open for subsequent accesses.
A memory array is written with corresponding input data
on DQ’s and DQM input logic level appearing at the same
time. Data will be written to memory when DQM signal is
LOW. When DQM is HIGH, the corresponding data inputs
will be ignored, and a WRITE will not be executed to that
byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
BA0, BA1 can be used to select which bank is precharged
or they are treated as “Don’t Care”. A10 determined
whether one or all banks are precharged. After execut-
is the period required for bank precharging. Once a bank
has been precharged, it is in the idle state and must be
activated prior to any READ or WRITE commands being
issued to that bank.
AUTO PRECHARGE
The AUTO PRECHARGE function ensures that the pre-
charge is initiated at the earliest valid stage within a burst.
This function allows for individual-bank precharge without
requiring an explicit command. A10 to enable the AUTO
6
RP
, which
PRECHARGE function in conjunction with a specific READ
or WRITE command. For each individual READ or WRITE
command, auto precharge is either enabled or disabled.
AUTO PRECHARGE does not apply except in full-page
burst mode. Upon completion of the READ or WRITE
burst, a precharge of the bank/row that is addressed is
automatically performed.
AUTO REFRESH COMMAND
This command executes the AUTO REFRESH operation.
The row address and bank to be refreshed are automatically
generatedduringthisoperation. Thestipulatedperiod(t
required for a single refresh operation, and no other com-
mands can be executed during this period. This command
is executed at least 4096 times for every T
AUTO REFRESH command, address bits are “Don’t Care”.
This command corresponds to CBR Auto-refresh.
BURST TERMINATE
The BURST TERMINATE command forcibly terminates
the burst read and write operations by truncating either
fixed-length or full-page bursts and the most recently
registered READ or WRITE command prior to the BURST
TERMINATE.
COMMAND INHIBIT
COMMAND INHIBIT prevents new commands from being
executed. Operations in progress are not affected, apart
from whether the CLK signal is enabled
NO OPERATION
When CS is low, the NOP command prevents unwanted
commands from being registered during idle or wait
states.
LOAD MODE REGISTER
During the LOAD MODE REGISTER command the mode
register is loaded from A0-A11. This command can only
be issued when all banks are idle.
ACTIVE COMMAND
When the ACTIVE COMMAND is activated, BA0, BA1
inputs selects a bank to be accessed, and the address
inputs on A0-A11 selects the row. Until a PRECHARGE
command is issued to the bank, the row remains open
for accesses.
Integrated Silicon Solution, Inc. - www.issi.com
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