IS42S32800D-75ETLI-TR ISSI, Integrated Silicon Solution Inc, IS42S32800D-75ETLI-TR Datasheet - Page 48

• Manufacturer Part Number: IS42S32800D-75ETLI-TR
• Description: IC SDRAM 256MBIT 133MHZ 86TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS42S32800D-75ETLI-TR

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 86-TSOPII
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS42S32800D, IS45S32800D
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by programming
the write burst mode bit (M9) in the mode register to a logic
1. In this mode, all WRITE commands result in the access
of a single column location (burst of one), regardless of
the programmed burst length. READ commands access
columns according to the programmed burst length and
sequence, just as in the normal mode of operation (M9
= 0).
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another bank
while an access command with auto precharge enabled is
executing is not allowed by SDRAMs, unless the SDRAM
supports CONCURRENT AUTO PRECHARGE. ISSI
READ With Auto Precharge interrupted by a READ
READ With Auto Precharge interrupted by a WRITE
48
Internal States
Internal States
COMMAND
COMMAND
ADDRESS
ADDRESS
BANK m
BANK m
BANK n
BANK n
DQM
CLK
CLK
DQ
DQ
READ - AP
BANK n,
T0
Page Active
T0
BANK n
COL a
NOP
Page Active
CAS Latency - 3 (BANK n)
BANK n,
READ - AP
COL a
BANK n
T1
T1
NOP
Page Active
Page Active
READ with Burst of 4
READ with Burst of 4
CAS Latency - 3 (BANK n)
T2
T2
NOP
NOP
BANK n,
READ - AP
COL b
BANK m
T3
T3
NOP
D
OUT
a
CAS Latency - 3 (BANK m)
SDRAMs support CONCURRENT AUTO PRECHARGE.
Four cases where CONCURRENT AUTO PRECHARGE
occurs are defined below.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto precharge):
2.Interrupted by a WRITE (with or without auto precharge):
Interrupt Burst, Precharge
A READ to bank m will interrupt a READ on bank n,
CAS latency later. The PRECHARGE to bank n will
begin when the READ to bank m is registered.
A WRITE to bank m will interrupt a READ on bank n
when registered.DQM should be used three clocks prior
to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to
bank m is registered.
WRITE - AP
BANK m,
BANK m
T4
T4
NOP
COL b
D
D
IN
t
OUT
RP - BANK n
READ with Burst of 4
b
a
Interrupt Burst, Precharge
WRITE with Burst of 4
T5
T5
D
NOP
NOP
D
IN
OUT
t
b+1
RP - BANK n
a+1
Integrated Silicon Solution, Inc. - www.issi.com
T6
T6
D
NOP
NOP
D
IN
OUT
b+2
b
DON'T CARE
DON'T CARE
Idle
T7
T7
D
NOP
NOP
D
Write-Back
IN
Precharge
OUT
b+3
t
t
RP - BANK m
DPL - BANK m
b+1
Idle
12/01/09
Rev. C