IS42S32160C-75BL-TR ISSI, Integrated Silicon Solution Inc, IS42S32160C-75BL-TR Datasheet
IS42S32160C-75BL-TR
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IS42S32160C-75BL-TR Summary of contents
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... Rev. B 01/22/09 JANUARY 2009 DESCRIPTION: The ISSI's IS42S32160C is a 512Mb Synchronous DRAM configured as a quad 4M x32 DRAM. It achieves high-speed data transfer using a pipeline architecture with a synchronous interface. All inputs and outputs sig- nals are registered on the rising edge of the clock input, CLK ...
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... IS42S32160C FUNCTIONAL BLOCK DIAGRAM 16Mbx16 SDRAM CLK CKE COMMAND CS DECODER RAS CAS & CLOCK WE MODE GENERATOR REGISTER 13 A10 A12 A11 ROW A0 ADDRESS BA0 LATCH BA1 13 COLUMN ADDRESS LATCH 9 BURST COUNTER COLUMN ADDRESS BUFFER FUNCTIONAL BLOCK DIAGRAM 16Mbx32 SDRAM CS CLK CKE# Die 01 ...
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... IS42S32160C PIN DESCRIPTIONS Symbol Type Description CLK Input Clock:CLK is driven by the system clock.All SDRAM input signals are sampled on the positive edge of CLK.CLK also increments the internal burst counter and controls the output registers. CKE Input Clock Enable:CKE activates(HIGH)and deactivates(LOW) the CLK signal.If CKE goes low syn- ...
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... IS42S32160C PIN CONFIGURATION PACKAGE CODE BALL FBGA (Top View) (8. 13.00 mm Body, 0.8 mm Ball Pitch PIN DESCRIPTIONS A0-A12 Row Address Input A0-A8 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ31 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select ...
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... IS42S32160C OPERATION MODE Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Truth table shows the operation commands. (1),(2) Truth Table Command State BankActivate Idle (3) BankPrecharge Any PrechargeAll Any Write Active (3) Write and Auto Precharge Active (3) Read Active ...
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... IS42S32160C I Commands 1 BankActivate (RAS#=”L”, CAS#=”H”, WE#=”H”, BS =Bank, A0-A12 =Row Address) The BankActivate command activates the idle bank designated by the BS0,1 (Bank Select) signal.By latching the row address A12 at the time of this command, the selected row access is initiated.The read or write operation in the same bank can occur after a time delay of tRCD(min ...
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... IS42S32160C 3 PrechargeAll command (RAS#=”L”, CAS#=”H”, WE#=”L”, BS =Don t care, A10 =”H”) The Precharge All command precharges all the four banks simultaneously and can be issued even if all banks are not in the active state. All banks are then switched to the idle state. ...
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... IS42S32160C T0 T1 CLK COMMAND READ A READ B CAS# latency=2 t CK2 , DQ- s CAS# latency=3 t CK3 , DQ- s Read Interrupted by a Read (Burst Length =4,CAS#Latency =2,3) The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from a Write command.The DQMs must be asserted (HIGH)at least two clocks prior to the Write command to suppress data-out on the DQ pins.To guarantee the DQ pins against I/O contention,a single cycle with high-impedance on the DQ pins must occur between the last read data and the Write command (refer to the following three figures) ...
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... IS42S32160C T0 T1 CLK COMMAND NOP READ A DQ’s : "H" or "L" Read to Write Interval (Burst Length = 4,CAS# Latency = CLK DQM COMMAND NOP NOP CAS# latency=2 tCK2, DQs : "H" or "L" Read to Write Interval (Burst Length = 4,CAS# Latency = CLK DQM COMMAND NOP NOP CAS# latency=2 t CK2 , DQ’ ...
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... IS42S32160C CLK Bank, ADDRESS Col A COMMAND READ A NOP CAS# latency=2 t CK2 , DQ's CAS# latency=3 t CK3 , DQ's Read to Precharge (CAS#Latency =2,3) 5 Write command (RAS#=”H”, CAS#=”L”, WE#=”L”, BS =Bank, A10 =”L”, A0-A8 =Column Address) The Write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank ...
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... IS42S32160C CLK COMMAND NOP WRITEA WRITEB 1 Clk Interval DIN A 0 DIN B 0 DQ’s Write Interrupted by a Write (Burst Length =4, CAS# Latency =2,3) The Read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid data contention, input data must be removed from the DQs at least one clock cycle before the first read data appears on the outputs (refer to Figure " ...
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... IS42S32160C CLK Bank, ADDRESS Col A COMMAND READ A NOP CAS# latency=2 t CK2 , DQ's CAS# latency=3 t CK3 , DQ's Read to Precharge (CAS#Latency =2,3) 5 Write command (RAS#=”H”, CAS#=”L”, WE#=”L”, BS =Bank, A10 =”L”, A0-A8 =Column Address) The Write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank ...
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... IS42S32160C I (iii) WRITE with Auto Precharge Interrupted by a READ Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out ap- pearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m ...
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... IS42S32160C 7 Mode Register Set command (RAS# =”L”, CAS# =”L”, WE# =”L”, BS0,1 and A12-A0 =Register Data) The mode register stores the data for controlling the various operating modes of SDRAM. The Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst Length in the Mode register to make SDRAM useful for a variety of different applications. The default values of the Mode Register after power-up are undefined ...
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... IS42S32160C The mode register is divided into various fields depending on functionality. Address BS0,1 A12-A10 A9 Function RFU* WBL *Note:RFU (Reserved for future use)should stay 0 during MRS cycle. Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length full page ...
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... IS42S32160C • Addressing Sequence of Interleave Mode A column access is started in the input column address and is performed by inverting the address bits in the sequence shown in the following table. Data n Data Data Data Data Data Data Data Data CAS# Latency Field (A6~A4) This field specifies the number of clock cycles from the assertion of the Read command to the first read data ...
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... IS42S32160C I Test Mode field (A8~A7) These two bits are used to enter the test mode and must be programmed to “00”in normal operation Write Burst Length (A9) This bit is used to select the burst write length No-Operation command (RAS# =”H”, CAS# =”H”, WE# =”H”) The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS# is Low) ...
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... IS42S32160C 10 Device Deselect command (CS# =”H”) The Device Deselect command disables the command decoder so that the RAS#,CAS#,WE# and Address inputs are ignored,regardless of whether the CLK is enabled.This command is similar to the No Operation command. 11 AutoRefresh command (RAS# =”L”, CAS# =”L”, WE# =”H”, CKE =”H”) The AutoRefresh command is used during normal operation of the SDRAM and is analogous to CAS#-before- RAS#(CBR)Refresh in conventional DRAMs ...
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... I IS42S32160C ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Supply Voltage (with respect Supply Voltage for Output (with respect to V DDQ V Input Voltage (with respect Output Voltage (with respect Short circuit output current CS P Power Dissipation ( D T Operating Temperature OPT T Storage Temperature STG Notes: 1 ...
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... IS42S32160C D.C. ELECTRICAL CHARACTERISTICS (RECOMMENDED OPERATING CONDITIONS) Description/ Test Condition Operating Current t t (min), Outputs Open, Input ≥ signal one transition per one cycle Precharge Standby Current in power down mode t = 15ns, CKE ≤ V (max Precharge Standby Current in power down mode ∞ ...
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... IS42S32160C E AC ELECTRICAL CHARACTERISTICS (RECOMMENDED OPERATING CONDITIONS) Symbol A.C. Parameter t Row cycle time RC (same bank) t Row activate to row activate delay RRD (different banks) t RAS# to CAS# delay RCD (same bank) t Precharge to refresh/row activate command RP (same bank) t Row activate to precharge time RAS (same bank) ...
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... IS42S32160C LVTTL Interface Reference Level of Output Signals Output Load Input Signal Levels Transition Time (Rise and Fall)of Input Signals Reference Level of Input Signals Z0= 50 Ω Output LVTTL A.C. Test Load 7. Transition times are measured between VIH and VIL.Transition(rise and fall) of input signals are in a fixed slope (1 ns) ...
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... IS42S32160C I Timing Waveforms AC Parameters for Write Timing (Burst Length=4, CAS# Latency= CLK CK2 CKE CS# RAS# CAS# WE# BS0 ADDR. RBx DQM t RCD Hi-Z DQ Activate Write with Command Auto Precharge Bank A Command Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/22/ T10 T11 T12 ...
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... IS42S32160C AC Parameters for Read Timing (Burst Length=2, CAS# Latency= CLK CKE t IS CS# RAS# CAS# WE# BS0,1 A10 RAx t IS ADD RAx DQM Hi-Z DQ Activate Command Bank CK2 RBx CAx RBx t RRD t RAS AC2 t AC2 t HZ RCD t LZ Ax0 Ax1 t OH Read Activate ...
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... IS42S32160C Auto Refresh (CBR)(Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 A10 ADD t RP DQM DQ DQ Precharge All Auto Refresh Command Command Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/22/ T10 T11 T12 T13 T14 RAx RAx Auto Refresh ...
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... IS42S32160C Power on Sequence and Auto Refresh (CBR CLK High level CKE is required CS RAS CAS WE BS0, 1 A10 ADD DQM High Level is Necessary t RP Hi-Z DQ Precharge 1st Auto Command Refresh Inputs All Banks Command must be stable for 200us T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
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... IS42S32160C I Self Refresh Entry & Exit Cycle CLK *Note 2 *Note 1 CKE t IS CS# RAS# *Note 8 CAS# BS0,1 ADD WE# DQM Hi-Z DQ SelfRefresh Enter Note:To Enter SelfRefresh Mode 1. CS#,RAS#&CAS#with CKE should be low at the same clock cycle. 2. After 1 clock cycle,all the inputs including the system clock can be don ’t care except for CKE. ...
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... IS42S32160C Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx ADD RAx CAx DQM DQ Hi-Z Activate Read Command Command Bank A Bank A Note:CKE to CLK disable/enable =1 clock T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
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... IS42S32160C I Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx ADD CAx RAx DQM DQ Hi-Z Hi-Z Read Activate Command Command Bank A Bank A Note:CKE to CLK disable/enable =1 clock Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev ...
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... IS42S32160C Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx ADD RAx CAx DQM Hi-Z DQ DAx0 Clock Suspend Activate 1 Cycle Command Bank A Write Command Bank A Note:CKE to CLK disable/enable =1 clock T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
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... IS42S32160C I Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx ADD RAx CAx DQM DQ Hi-Z DAx0 Clock Suspend ...
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... IS42S32160C Power Down Mode and Clock Mask (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 RAx A10 ADD RAx DQM Hi-Z DQ ACTIVE STANDBY Activate Command Bank A Power Down Mode Entry T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
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... IS42S32160C Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS# RAS# CAS# WE# BA0,1 A10 RAw ADD CAw RAw DQM Hi-Z DQ Activate Read Command ...
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... IS42S32160C Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAw ADD RAw CAw DQM Hi-Z DQ Activate Read Command ...
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... IS42S32160C Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 RBw A10 ADD CBw RBw DQM Hi-Z DQ DBw0 DBw1 DBw2 DBw3 ...
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... IS42S32160C Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T2 2 CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RBw ADD RBw DQM Hi-Z DBw0 DQ Activate Command Command ...
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... IS42S32160C Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 RBx A10 RBx CBx ADD t t RCD AC3 DQM Hi-Z DQ Activate ...
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... IS42S32160C Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx ADD RAx CAx t RCD DQM Hi-Z DQ DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 ...
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... IS42S32160C Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RAx CAx ADD t RCD DQM Hi-Z DQ DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 ...
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... IS42S32160C Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx ADD RAx CAx t RCD DQM Hi-Z DQ DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 ...
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... IS42S32160C Read and Write Cycle (Burst Length=4, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx ADD RAx CAx DQM Hi-Z DQ Activate Read Command Command Bank A Bank A Integrated Silicon Solution, Inc. — ...
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... IS42S32160C Interleaving Column Read Cycle (Burst Length=4, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 RAx A10 ADD RAx CAy t t RCD DQM Hi-Z DQ Read Activate Command Command ...
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... IS42S32160C Interleaved Column Read Cycle (Burst Length=4, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 RAx A10 RAx CAx ADD t RCD DQM DQ Hi-Z Read Activate Command Command Bank A Bank A Integrated Silicon Solution, Inc. — ...
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... IS42S32160C Interleaved Column Write Cycle (Burst Length=4, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 RAx A10 RAx CAx ADD t RCD DQM t RRD Hi-Z DAx0 DAx1 DAx2 DAx3 ...
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... IS42S32160C Interleaved Column Write Cycle (Burst Length=4, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 RAx RBw A10 RAx CAx RBw ADD t RCD DQM t > t RRD RRD(min) Hi-Z ...
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... IS42S32160C Auto Precharge after Read Burst (Burst Length=4, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 High CKE CS# RAS# CAS# WE# BS0,1 RAx RBx A10 RBx RAx CAx ADD DQM Hi-Z DQ Ax0 Activate ...
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... IS42S32160C Auto Precharge after Read Burst (Burst Length=4, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 RAx RBx A10 CAx RAx RBx ADD DQM Hi-Z DQ Activate Activate ...
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... IS42S32160C Auto Precharge after Write Burst (Burst Length=4, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 High CKE CS# RAS# CAS# WE# BS0,1 RAx A10 CAx ADD RAx DQM Hi-Z DQ DAx0 DAx1 DAx2 DAx3 ...
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... IS42S32160C Auto Precharge after Write Burst (Burst Length=4, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 RBx RAx A9 ADD RAx RBx CAx DQM Hi-Z DAx0 DAx1 DAx2 DAx3 ...
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... IS42S32160C Full Page Read Cycle (Burst Length=Full Page, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 High CKE CS# RAS# CAS# WE# BS0,1 RAx A10 ADD RAx CAx DQM Hi-Z DQ Read Activate Activate Command ...
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... IS42S32160C Full Page Read Cycle (Burst Length=Full Page, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 RAx A10 ADD RAx CAx DQM DQ Hi-Z Read Activate Command Command ...
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... IS42S32160C Full Page Write Cycle (Burst Length=Full Page, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 High CKE CS# RAS# CAS# WE# BS0,1 RAx A10 ADD RAx CAx DQM Hi-Z DQ DAx DAx+1 DAx+2 DAx+3 DAx-1 ...
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... IS42S32160C Full Page Write Cycle (Burst Length=Full Page, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE High CS# RAS# CAS# WE# BS0,1 RAx RBx A10 ADD RAx CAx RBx DQM Hi-Z DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx ...
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... IS42S32160C Byte Write Operation (Burst Length=4, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 High CKE CS# RAS# CAS# WE# BS0,1 A10 RAx ADD RAx CAx DQM0 DQM1,2,3 DQ0 - DQ7 DQ8 - DQ15 Read Activate ...
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... IS42S32160C Full Page Random Column Read (Burst Length=Full Page, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T2 2 CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RBx RAx RBx CAx CBx CAy ADD DQM t t RRD ...
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... IS42S32160C Full Page Random Column Write (Burst Length=Full Page, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 RAx RBx A10 ADD RAx RBx CAx DQM t t RRD RCD ...
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... IS42S32160C Precharge Termination of a Burst (Burst Length=8 or Full Page, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS# RAS# CAS# WE# BS0,1 RAx A10 RAx CAx ADD DQM DQ DAx0 DAx1 DAx2 DAx3 ...
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... IS42S32160C Precharge Termination of a Burst (Burst Length=4,8 or Full Page, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 RAx A10 RAx CAx ADD DQM DQ DAx0 Write Activate Command ...
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... IS42S32160C-75BL 166 MHz 6.0 IS42S32160C-6BL Industrial Range: -40°C to 85°C Frequency Speed (ns) Order Part No. 133 MHz 7.5 IS42S32160C-75BLI 166 MHz 6.0 IS42S32160C-6BI 166 MHz 6.0 IS42S32160C-6BLI Integrated Silicon Solution, Inc. Rev. B 01/22/09 = 3.3V dd Package 8x13mm BGA, Lead-free 8x13mm BGA, Lead-free Package ...
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