M45PE20-VMP6G NUMONYX, M45PE20-VMP6G Datasheet - Page 24

• Manufacturer Part Number: M45PE20-VMP6G
• Description: IC FLASH 2MBIT 75MHZ 8VFQFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M45PE20-VMP6G

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 2M (256K x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VFQFN, 8-VFQFPN
• Memory Configuration: 256K X 8
• Ic Interface Type: Serial, SPI
• Clock Frequency: 25MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: VDFPN
• No. Of Pins: 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Instructions
6.7
24/47
Page write (PW)
The page write (PW) instruction allows bytes to be written in the memory. Before it can be
accepted, a write enable (WREN) instruction must previously have been executed. After the
write enable (WREN) instruction has been decoded, the device sets the write enable latch
(WEL).
The page write (PW) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, three address bytes and at least one data byte on serial data input (D). The
rest of the page remains unchanged if no power failure occurs during this write cycle.
The page write (PW) instruction performs a page erase cycle even if only one byte is
updated.
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding
the addressed page boundary wrap round, and are written from the start address of the
same page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip Select
(S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be written correctly within the same page. If less than
256 Data bytes are sent to device, they are correctly written at the requested addresses
without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the page write (PW) instruction to write all
consecutive targeted bytes in a single sequence versus using several page write (PW)
sequences with each containing only a few bytes (see
operation)
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the page write (PW) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed page write cycle (whose duration is
t
check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during
the self-timed page write cycle, and is 0 when it is completed. At some unspecified time
before the cycle is complete, the write enable latch (WEL) bit is reset.
A page write (PW) instruction applied to a page that is hardware protected is not executed.
Any page write (PW) instruction, while an erase, program or write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
PW
) is initiated. While the page write cycle is in progress, the status register may be read to
and
Table 15: AC characteristics (75 MHz operation, T9HX (0.11 µm)
Figure
12.
Table 14: AC characteristics (50 MHz
process)).
M45PE20