M25P16-VME6TG NUMONYX, M25P16-VME6TG Datasheet - Page 21

• Manufacturer Part Number: M25P16-VME6TG
• Description: IC FLASH 16MBIT 75MHZ 8VDFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P16-VME6TG

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 16M (2M x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VDFPN
• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 15ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VDFPN EP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 8mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25P16-VME6TG; M25P16-VME6TGTR

6.4
6.4.1
6.4.2
6.4.3
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Program, Erase or Write Status
Register cycle is in progress. When one of these cycles is in progress, it is recommended to
check the Write In Progress (WIP) bit before sending a new instruction to the device. It is
also possible to read the Status Register continuously, as shown in
Table 6.
The status and control bits of the Status Register are as follows:
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to ‘1’, such a cycle is in progress, when reset to
‘0’ no such cycle is in progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to ‘1’ the internal Write Enable Latch is set, when set to ‘0’ the internal Write
Enable Latch is reset and no Write Status Register, Program or Erase instruction is
accepted.
BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to
be software protected against Program and Erase instructions. These bits are written with
the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,
BP1, BP0) bits is set to ‘1’, the relevant memory area (as defined in
protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect
(BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not
been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2,
BP1, BP0) bits are 0.
Status Register Write Protect
SRWD
b7
Status Register format
0
0
BP2
BP1
Block Protect bits
Write Enable Latch bit
BP0
Figure
Table
WEL
Write In Progress bit
2) becomes
11.
WIP
b0
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