M25P16-VMN6TP NUMONYX, M25P16-VMN6TP Datasheet - Page 12
![IC FLASH 16MBIT 75MHZ 8SOIC](/photos/7/28/72833/m25p16-vmn6tp_sml.jpg)
M25P16-VMN6TP
Manufacturer Part Number
M25P16-VMN6TP
Description
IC FLASH 16MBIT 75MHZ 8SOIC
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.M25P16-VMN6P.pdf
(59 pages)
Specifications of M25P16-VMN6TP
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
16M (2M x 8)
Speed
75MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Package
8SOIC N
Cell Type
NOR
Density
16 Mb
Architecture
Sectored
Block Organization
Symmetrical
Typical Operating Supply Voltage
3.3 V
Sector Size
64KByte x 32
Timing Type
Synchronous
Interface Type
Serial-SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
M25P16-VMN6TP
M25P16-VMN6TPTR
M25P16-VMN6TPTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25P16-VMN6TP
Manufacturer:
ISSI
Quantity:
2 300
Company:
Part Number:
M25P16-VMN6TP
Manufacturer:
Numonyx
Quantity:
30 000
Company:
Part Number:
M25P16-VMN6TP
Manufacturer:
MICRON
Quantity:
317
Part Number:
M25P16-VMN6TP
Manufacturer:
ST
Quantity:
20 000
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Operating features
Page programming
To program one data byte, two instructions are required: Write Enable (WREN), which is
one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This
is followed by the internal Program cycle (of duration t
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be
programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see
Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be
applied, the bytes of memory need to have been erased to all 1s (FFh). This can be
achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the
entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of
duration t
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
Polling during a Write, Program or Erase cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase
(SE or BE) can be achieved by not waiting for the worst case delay (t
Write In Progress (WIP) bit is provided in the Status Register so that the application program
can monitor its value, polling it to establish when the previous Write cycle, Program cycle or
Erase cycle is complete.
Active Power, Standby Power and Deep Power-down modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the Active
Power mode until all internal cycles have completed (Program, Erase, Write Status
Register). The device then goes in to the Standby Power mode. The device consumption
drops to I
The Deep Power-down mode is entered when the specific instruction (the Deep Power-
down (DP) instruction) is executed. The device consumption drops further to I
device remains in this mode until another specific instruction (the Release from Deep
Power-down and Read Electronic Signature (RES) instruction) is executed.
While in the Deep Power-down mode, the device ignores all Write, Program and Erase
instructions (see
mechanism, when the device is not in active use, to protect the device from inadvertent
Write, Program or Erase instructions.
SE
CC1
or t
.
BE
Deep Power-down
).
(DP)). This can be used as an extra software protection
PP
).
W
Page Program
, t
PP
, t
SE
CC2
, or t
. The
BE
(PP)).
). The