M45PE80-VMP6G NUMONYX, M45PE80-VMP6G Datasheet

IC FLASH 8MBIT 50MHZ 8VFQFPN

M45PE80-VMP6G

Manufacturer Part Number
M45PE80-VMP6G
Description
IC FLASH 8MBIT 50MHZ 8VFQFPN
Manufacturer
NUMONYX
Series
Forté™r
Datasheet

Specifications of M45PE80-VMP6G

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
8M (1M x 8)
Speed
50MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-VFQFN, 8-VFQFPN
Ic Interface Type
Serial, SPI
Clock Frequency
75MHz
Supply Voltage Range
2.7V To 3.6V
No. Of Pins
8
Operating Temperature Range
-40°C To +85°C
Voltage, Vcc
3V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M45PE80-VMP6G
Manufacturer:
MICROCHIP
Quantity:
3 000
Part Number:
M45PE80-VMP6G
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
M45PE80-VMP6G
Manufacturer:
ST
0
Part Number:
M45PE80-VMP6G
Manufacturer:
MICRON/美光
Quantity:
20 000
Part Number:
M45PE80-VMP6G-N
Manufacturer:
STMicroelectronics
Quantity:
500
Features
December 2008
SPI bus compatible serial interface
75 MHz clock rate (maximum)
2.7 V to 3.6 V single supply voltage
8 Mbit of Page-Erasable Flash memory
Page size: 256 bytes:
– Page Write in 11 ms (typical)
– Page Program in 0.8 ms (typical)
– Page Erase in 10 ms (typical)
Sector Erase (64 Kbytes)
Hardware Write protection of the bottom sector
(64 Kbytes)
Electronic signature
– JEDEC standard two-byte signature
Unique ID code (UID) with 16 bytes read only,
available upon customer request only on T9HX
process technology parts
Deep Power-down mode 1 μA (typical)
More than 100 000 Write cycles
More than 20 years’ data retention
Packages
– RoHS compliant
(4014h)
8 Mbit, low voltage, Page-Erasable Serial Flash memory
with byte alterability and a 75 MHz SPI bus interface
Rev 11
6 × 5 mm (MLP8)
VFQFPN8 (MP)
150 mils width
MLP8 6 x 5 mm
SO8N (MN)
QFN8L (MS)
M45PE80
208 mils width
SO8W (MW)
www.numonyx.com
1/48
1

Related parts for M45PE80-VMP6G

M45PE80-VMP6G Summary of contents

Page 1

... Deep Power-down mode 1 μA (typical) More than 100 000 Write cycles More than 20 years’ data retention Packages – RoHS compliant December 2008 VFQFPN8 (MP) 6 × (MLP8) SO8N (MN) 150 mils width QFN8L (MS) MLP8 Rev 11 M45PE80 SO8W (MW) 208 mils width 1/48 1 www.numonyx.com ...

Page 2

... Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 13 4.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 Active Power, Stand-by Power and Deep Power-Down modes . . . . . . . . 13 4.7 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Identification (RDID 6.4 Read Status Register (RDSR) ...

Page 3

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

... List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4. Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 5. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 6. Power-Up timing and VWI threshold Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 8. Operating conditions Table 9. AC measurement conditions Table 10. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 11. ...

Page 5

... List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. VFQFPN and SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 6. Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 8. Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 20 Figure 9 ...

Page 6

... Summary description The M45PE80 Mbit (1 Mbit × 8 bit) Serial Paged Flash Memory accessed by a high speed SPI-compatible bus. The memory can be written or programmed 1 to 256 bytes at a time, using the Page Write or Page Program instruction. The Page Write instruction consists of an integrated Page Erase cycle followed by a Page Program cycle ...

Page 7

... Figure 2. VFQFPN and SO connections 1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally and must not be allowed to be connected to any other voltage or signal line on the PCB See Section 11: Package mechanical M45PE80 Reset AI06811B for package dimensions, and how to identify pin-1. ...

Page 8

... This input signal puts the device in the Hardware Protected mode, when Write Protect (W) is connected causing the first 256 pages of memory to become read-only by protecting SS them from write, program and erase operations. When Write Protect (W) is connected the first 256 pages of memory behave like the other pages of memory. CC 8/48 ...

Page 9

V supply voltage the supply voltage. CC 2.8 V ground the reference for the V SS supply voltage. CC 9/48 ...

Page 10

... Serial Data Output (Q) line at a time, the other devices are high impedance. Resistors R (represented in that the M45PE80 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at ...

Page 11

Example pF, that is R*C p Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 μs. Figure 4. SPI modes supported CPOL CPHA ...

Page 12

... All of this buffer management is handled internally, and is transparent to the user. The user is given the facility of being able to alter the contents of the memory on a byte-by-byte basis. For optimized timings recommended to use the Page Write (PW) instruction to write all ...

Page 13

A fast way to modify data The Page Program (PP) instruction provides a fast way of modifying data up to 256 contiguous bytes at a time, provided that it involves only resetting bits to 0 that had previously been ...

Page 14

... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M45PE80 boasts the following data protection mechanisms: Power-On Reset and an internal timer (t inadvertent changes while the power supply is outside the operating specification. ...

Page 15

... Memory organization The memory is organized as: 4096 pages (256 bytes each). 1 048 576 bytes (8 bits each) 16 sectors (512 Kbits, 65536 bytes each) Each page can be individually: programmed (bits are programmed from erased (bits are erased from written (bits are changed to either The device is Page or Sector Erasable (bits are erased from 0 to 1). ...

Page 16

Figure 5. Block diagram Reset W Control Logic Address Register and Counter 16/48 High Voltage Generator I/O Shift Register 256 Byte Data Buffer 10000h 00000h 256 Bytes (Page Size) X Decoder Status Register FFFFFh First 256 ...

Page 17

... High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write cycle, Program cycle or Erase cycle are ignored, and the internal Write cycle, Program cycle or Erase cycle continues unaffected ...

Page 18

Write Enable (WREN) The Write Enable (WREN) instruction The Write Enable Latch (WEL) bit must be set prior to every Page Write (PW), Page Program (PP), Page Erase (PE), and Sector Erase (SE) instruction. The Write Enable (WREN) instruction ...

Page 19

... The Read Identification (RDID) instruction allows the device identification data to be read as explained here, with the data values shown in sequence. Manufacturer identification (1 byte): Numonyx value assigned by JEDEC. Device identification (2 bytes): assigned by the device manufacturer. – The first byte indicates the memory type. ...

Page 20

... Status Register continuously, as shown in The status bits of the Status Register are as follows: 6.4.1 WIP bit The Write In Progress (WIP) bit indicates whether the memory is busy with a Write, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset such cycle is in progress. 6.4.2 WEL bit The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch ...

Page 21

... The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely ...

Page 22

... The instruction sequence is shown in The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely ...

Page 23

... Address bits A23 to A20 are Don’t Care. 6.7 Page Write (PW) The Page Write (PW) instruction allows bytes to be written in the memory. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL) ...

Page 24

If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be written correctly within the same page. If less than 256 Data bytes are sent to ...

Page 25

... Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from only). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...

Page 26

Figure 13. Page Program (PP) instruction sequence Data Byte MSB 1. Address bits A23 to A20 are Don’t Care 2. 1 ≤ n ≤ 256 ...

Page 27

Page Erase (PE) The Page Erase (PE) instruction sets to 1 (FFh) all bits inside the chosen page. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction ...

Page 28

Sector Erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction ...

Page 29

Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the ...

Page 30

Release from Deep Power-down (RDP) To exit from Deep Power-down mode, the Release from Deep Power-down (RDP) instruction must be issued. No other instruction must be issued while the device is in this mode. The Release from Deep Power-down ...

Page 31

Power-up and Power-down At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at Power-up, and then for a further delay ...

Page 32

Figure 18. Power-up timing (max (min) Reset State of the Device V WI Table 6. Power-Up timing and V Symbol ( (min low VSL CC (1) t Time delay before ...

Page 33

... CC V Electrostatic Discharge Voltage (Human Body Model) ESD 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn- assembly), the Numonyx RoHS complian 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω) Parameter (2) Min ...

Page 34

DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the ...

Page 35

Table 11. DC characteristics Symbol Parameter I Input leakage current LI I Output leakage current LO Standby current (Standby I CC1 and Reset modes) I Deep Power-down current CC2 Operating current I CC3 (FAST_READ) I Operating current (PW) CC4 I ...

Page 36

Table 12. AC characteristics (33 MHz operation) Test conditions specified in Symbol Alt. Clock frequency for the following instructions FAST_READ, PW, PP, PE, SE, DP, RDID RDP, WREN, WRDI, RDSR f Clock frequency for READ instructions ...

Page 37

Table 13. AC characteristics (50 MHz operation) Test conditions specified in Symbol Alt. Clock frequency for the following instructions FAST_READ, PW, PP, PE, SE, DP, RDP WREN, WRDI, RDSR, RDID f Clock frequency for READ instructions ...

Page 38

Table 14. AC characteristics (75 MHz operation) Test conditions specified in Symbol Alt. Clock frequency for the following instructions FAST_READ, RDLR, PW, PP, WRLR, PE, SE SSE, DP, RDP, WREN, WRDI, RDSR, WRCR f Clock frequency ...

Page 39

Figure 20. Serial input timing S tCHSL C tDVCH MSB IN D High Impedance Q Figure 21. Write Protect setup and hold timing W tWHSL High Impedance Q Figure 22. Output timing S C tCLQV tCLQX tCLQX ...

Page 40

Table 15. Reset conditions Symbol Alt. ( Reset Pulse Width RLRH RST Chip Select High to t SHRH Reset High 1. Value guaranteed by characterization, not 100% tested in production. Table 16. Timings after a Reset Low pulse ...

Page 41

Package mechanical Figure 24. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead, 6 × 5 mm, package outline Drawing is not to scale. 2. The circle in the top ...

Page 42

Figure 25. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, package outline b 1. Drawing is not to scale. 2. The circle in the top view of the package indicates the position of pin 1. Table ...

Page 43

Figure 26. SO8N - 8 lead Plastic Small Outline, 150 mils body width, package outline Drawing is not to scale. Table 19. SO8N - 8 lead Plastic Small Outline, 150 mils body ...

Page 44

Figure 27. QFN8L (MLP8) 8-lead, dual flat package no lead, 6 × 5 mm, package outline Drawing is not to scale. Table 20. QFN8L (MLP8) 8-lead dual flat package no lead ...

Page 45

... Numonyx Sales Office. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. M45PE80 – ...

Page 46

... Reference AN1995: Serial Flash Memory Device Marking. 14 Revision history Table 22. Document revision history Date Version 10-Feb-2003 1.0 02-Apr-2003 1.1 08-Apr-2003 1.2 05-May-2003 1.3 04-Jun-2003 1.4 26-Nov-2003 2.0 23-Jan-2004 3.0 28-May-2004 4.0 10-May-2005 5.0 4-Oct-2005 6.0 14-Feb-2006 46/48 Document written VFQFPN8 (MLP) package added ...

Page 47

... Table 15: Reset conditions updated. pulse SO8N package added (T9HX technology only), SO8W and VFQFPN8 package specifications updated (see 10-Dec-2007 9 Applied Numonyx branding. Added frequency MHz frequency, including characteristics (75 MHz Added new package, including 11-Nov-2008 10 flat package no lead, 6 × 5 mm, package outline (MLP8) 8-lead dual flat package no lead package mechanical data ...

Page 48

... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...

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