M25PE80-VMW6TG NUMONYX, M25PE80-VMW6TG Datasheet - Page 43

• Manufacturer Part Number: M25PE80-VMW6TG
• Description: IC FLASH 8MBIT 75MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25PE80-VMW6TG

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC W
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 8mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25PE80-VMW6TG; M25PE80-VMW6TGTR

M25PE80
6.15
Bulk erase (BE)
The bulk erase (BE) instruction sets all bits to ‘1’ (FFh). Before it can be accepted, a write
enable (WREN) instruction must previously have been executed. After the write enable
(WREN) instruction has been decoded, the device sets the write enable latch (WEL).
The bulk erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on serial data input (D). Chip Select (S) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the bulk erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed bulk erase cycle (whose duration is t
bulk erase cycle is in progress, the status register may be read to check the value of the
write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed bulk
erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the write enable latch (WEL) bit is reset.
Any bulk erase (BE) instruction, while an erase, program or write cycle is in progress, is
rejected without having any effects on the cycle that is in progress. A bulk erase (BE)
instruction is ignored if at least one sector or subsector is write-protected (Hardware or
software protection).
If Reset (Reset) is driven Low while a bulk erase (BE) cycle is in progress, the bulk erase
cycle is interrupted and data may not be erased correctly (see
a Reset Low
t
For the value of t
AC
Figure 21. Bulk erase (BE) instruction sequence
RHSL
parameters.
is then required before the device can be re-selected by driving Chip Select (S) Low.
pulse). On Reset going Low, the device enters the reset mode and a time of
RHSL
S
C
D
see
Table 26: Timings after a Reset Low pulse
0
Figure
1
2
Instruction
21.
3
4
5
6
7
Table 15: Device status after
AI03752D
BE
) is initiated. While the
in
Section 11: DC and
Instructions
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