M25PX64SOVZM6TP NUMONYX, M25PX64SOVZM6TP Datasheet - Page 49

• Manufacturer Part Number: M25PX64SOVZM6TP
• Description: IC FLASH 64MBIT 75MHZ 24TBGA
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25PX64SOVZM6TP

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 64M (8M x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-TBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25PX64SOVZM6TPTR

6.16
Sector erase (SE)
The sector erase (SE) instruction sets to ‘1’ (FFh) all bits inside the chosen sector. Before it
can be accepted, a write enable (WREN) instruction must previously have been executed.
After the write enable (WREN) instruction has been decoded, the device sets the write
enable latch (WEL).
The sector erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on serial data input (DQ0). Any address inside the
sector (see
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the sector erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed sector erase cycle (whose duration is t
initiated. While the sector erase cycle is in progress, the status register may be read to
check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during
the self-timed sector erase cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the write enable latch (WEL) bit is reset.
A sector erase (SE) instruction applied to a page which is protected by the block protect
(BP2, BP1, BP0) bits (see
Figure 25. Sector erase (SE) instruction sequence
1. Address bit A23 is don’t care.
Table
S
C
DQ1
4) is a valid address for the sector erase (SE) instruction. Chip Select (S)
Table 3
0
1
2
and
Instruction
3
Figure
Table
4
5
6
25.
4) is not executed.
7
MSB
23 22
8
9
24-bit address
2
29 30 31
(1)
1
0
AI13742b
SE
) is
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