M95256-RMN6P STMicroelectronics, M95256-RMN6P Datasheet - Page 19
![IC EEPROM 256KBIT 2MHZ 8SOIC](/photos/1/38/13851/497-8-soic_sml.jpg)
M95256-RMN6P
Manufacturer Part Number
M95256-RMN6P
Description
IC EEPROM 256KBIT 2MHZ 8SOIC
Manufacturer
STMicroelectronics
Datasheet
1.M95256-WMN6TP.pdf
(47 pages)
Specifications of M95256-RMN6P
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
256K (32K x 8)
Speed
2MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-6353-5
M95256-DR, M95256, M95256-W, M95256-R
5.5
Figure 9.
Read from Memory Array (READ)
As shown in
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data output (Q).
If Chip Select (S) continues to be driven low, the internal address register is automatically
incremented, and the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within any page.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
S
C
D
Q
Write Status Register (WRSR) sequence
Figure
10, to send this instruction to the device, Chip Select (S) is first driven
0
1
High Impedance
Doc ID 12276 Rev 13
2
Instruction
3
4
5
6
7
MSB
7
8
6
9 10 11 12 13 14 15
5
Register In
4
Status
3
2
1
0
AI02282D
Instructions
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