N25Q128A11B1241F NUMONYX, N25Q128A11B1241F Datasheet
N25Q128A11B1241F
Specifications of N25Q128A11B1241F
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N25Q128A11B1241F Summary of contents
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... Additional 2 Extended Device ID (EDID) bytes to identify device factory options – Unique ID code (UID) with 14 bytes read- only, available upon customer request 100,000 + program/erase cycles per sector More than 20 years data retention Packages – RoHS compliant Rev 1.0 N25Q128 SO16 (SF) 300 mils width 1/185 www.numonyx.com 1 ...
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Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Dual Command Fast reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.3 ...
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... Program Suspend Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.5.7 Protection Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.1 SPI Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.2 Specific hardware and software protection . . . . . . . . . . . . . . . . . . . . . . . . 48 8 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.1 Extended SPI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.1.1 Read Identification (RDID 9.1.2 Read Data Bytes (READ 9.1.3 Read Data Bytes at Higher Speed (FAST_READ ...
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Program OTP instruction (POTP 9.1.17 Subsector Erase (SSE) . ...
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Read Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 ...
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... Enter XIP mode by setting the Non Volatile Configuration Register . . . . 162 10.2 Enter XIP mode by setting the Volatile Configuration Register . . . . . . . 164 10.3 XIP mode hold and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 10.4 XIP Memory reset after a controller reset . . . . . . . . . . . . . . . . . . . . . . . . 166 11 Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.1 Fast POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 11.2 Rescue sequence in case of power loss during WRNVCR ...
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... Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 9. Software protection truth table (Sectors 0 to 255, 64 Kbyte Table 10. Protected area sizes (TB bit = Table 11. Protected area sizes (TB bit = Table 12. Memory organization (uniform Table 13. Memory organization (bottom Table 14. Memory organization (top Table 15. Instruction set: extended SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 16. ...
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... Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 2. VDFPN8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 3. SO16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 4. BGA connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 5. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 6. Extended SPI protocol example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 7. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 8. Non Volatile and Volatile configuration Register Scheme . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 9. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 10 ...
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Figure 49. Dual Command Page Program instruction sequence DSP, 02h . . . . . . . . . . . . . . . . . . . 118 Figure 50. Dual Command Page Program instruction sequence DSP, A2h ...
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Figure 101. Deep Power-down instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... The boot sectors can be erased a 4-Kbyte subsector at a time 64-Kbyte sector at a time. The entire memory can be also erased at a time or by sector. ...
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... Many different N25Q128 configurations are available, please refer to the ordering scheme page for the possibilities. Additional features are available as security options (The Security features are described in a dedicated Application Note). Please contact your nearest Numonyx Sales office for more information. Figure 1. Logic diagram Note: Reset functionality is available in devices with a dedicated part number ...
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Note: There is an exposed central pad on the underside of the VDFPN8 package. This is pulled, internally, to VSS, and must not be connected to any other voltage or signal line on the PCB. Figure 2. VDFPN8 connections 1. ...
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Figure 4. BGA connections Connect. 2. See Figure 116.: TBGA - mm, 24-ball, mechanical package ...
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Signal descriptions 2.1 Serial data output (DQ1) This output signal is used to transfer data serially out of the device. Data are shifted out on the falling edge of Serial Clock (C). When used as an Input ...
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... When Reset (Reset) is driven High, the memory is in the normal operating mode. When Reset (Reset) is driven Low, the memory will enter the Reset mode. In this mode, the output is high impedance. Driving Reset (Reset) Low while an internal operation is in progress will affect this operation (write, program or erase cycle) and data may be lost ...
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... W or VPP are selected by the voltage range applied to the pin. If the W/VPP input is kept in a low voltage range ( VCC) the pin is seen as a control input. This input signal is used to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP[0:3] bits of the Status Register. (See Table 3 ...
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... The difference between the two modes, as shown in bus master is in standby mode and not transferring data: C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1) Figure 5. Bus master and memory devices on the SPI bus SDO SPI interface with SDI (CPOL, CPHA) = ...
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SPI bus in high impedance. Example pF, that is R*C p master never leaves the SPI ...
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... SPI Protocols The N25Q128 memory can work with 3 different Serial protocols: Extended SPI protocol. Dual I/O SPI (DIO-SPI) protocol. Quad I/O SPI (QIO-SPI) protocol possible to choose among the three protocols by means of user volatile or non-volatile configuration bits.It's not possible to mix Extended SPI, DIO-SPI, and QIO-SPI protocols. ...
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Quad SPI (QIO-SPI) protocol Quad SPI (QIO-SPI) protocol: instructions, addresses, and I/O data are always transmitted on four data lines DQ0, DQ1, W/VPP(DQ2), and HOLD / (DQ3). The exception is the Program/Erase cycle performed with the VPP, in which ...
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... Read Operations To read the memory content in Extended SPI protocol different instructions are available: READ, Fast Read, Dual Output Fast Read, Dual Input Output Fast Read, Quad Output Fast Read and Quad Input Output Fast read, allowing the application to choose an instruction to send addresses and receive data by one, two or four data lines ...
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... Write, Program or Erase cycle is complete. The information on the memory being in progress for a Program, Erase, or Write instruction can be checked either on the Write In Progress (WIP) bit of the Status Register or in the Program/Erase Controller bit of the Flag Status Register ...
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When Chip Select (S) is High, the device is deselected, but could remain in the active power mode until all internal cycles have completed (program, erase, write status register). The device then goes in to the standby power mode. The ...
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Table 2. Device Status after Reset Low Pulse Conditions: reset pulse occurred (1) While decoding an instruction : WREN, WRDI, RDID, RDSR, READ, RDLR, Fast_Read, DOFR, DIOFR, QOFR, QIOFR, WRLR, PW, PP, PE, SE, BE, SSE, DP, RDP Under completion ...
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... Dual Command Fast reading Reading the memory data multiplexing the instruction, the addresses and the output data on 2 data lines can be achieved in DIO-SPI protocol by mean of the Dual Command Fast Read instruction, that has 3 instruction codes (BBh, 3Bh and 0Bh) to help the application code porting from Extended SPI protocol to DIO-SPI protocol ...
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... Subsector Erase, Sector Erase and Bulk Erase Similar to the Extended SPI protocol, in the DIO-SPI protocol to erase the memory bytes to all 1s (FFh) the Subsector Erase (SSE), the Sector Erase (SE) and the Bulk Erase (BE) instructions are available. These instructions start an internal Erase cycle (of duration tSSE, tSE or tBE) ...
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... The Dual and Single I/O Program instructions are not available in QIO-SPI protocol Programming the memory by multiplexing the instruction, the addresses and the output data on 4 wires can be achieved in QIO-SPI protocol by mean of the Quad Command Page Program instruction, that has 3 instruction codes (02h, 12h and 32h) to help the application code porting from Extended SPI protocol to QIO-SPI protocol ...
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... Subsector Erase, Sector Erase and Bulk Erase Similar to the Extended SPI protocol, Subsector Erase (SSE)(1), the Sector Erase (SE) and the Bulk Erase (BE) instructions are used to erase the memory in the QIO-SPI protocol. These instructions start an internal Erase cycle (of duration tSSE, tSE or tBE). ...
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... The HOLD (Hold) feature (or Reset feature, for parts having the reset functionality instead of hold) is disabled in QIO-SPI protocol when the device is selected: the Hold (or Reset)/ DQ3 pin always behaves as an I/O pin (DQ3 function) when the device is deselected. For parts with reset functionality still possible to reset the memory when it is deselected (C signal high). 5.3.9 ...
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... Please note that on the next power on the memory will start again in the working protocol set by the Non Volatile Register parameters. ...
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... Each register can be read and modified by means of dedicated instructions in all the 3 protocols (Extended SPI, DIO-SPI, and QIO-SPI). Reading time for all registers is comparable; writing time instead is very different: NVCR bits are set as Flash Cell memory content requiring a longer time to perform internal writing cycles. See Table 33.: AC Characteristics ...
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... SRWD Status register write protect 6.1.1 WIP bit The Write In Progress (WIP) bit set to 1 indicates that the memory is busy with a Write Status Register, Program or Erase cycle. 0 indicates no cycle is in progress. 6.1.2 WEL bit The Write Enable Latch (WEL) bit set to 1 indicates that the internal Write Enable Latch is set ...
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... Non Volatile Configuration Register The Non Volatile Configuration Register (NVCR) bits affects the default memory configuration after power-on. It can be used to make the memory start in the configuration to fit the application requirements. The device is delivered with Non Volatile Configuration Register (NVCR) bits all erased to 1 (FFFFh) ...
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Table 4. Non-Volatile Configuration Register Bit Parameter 0000 0001 0010 0011 0100 0101 0110 0111 1000 Dummy clock NVCR<15:12> 1001 cycle 1010 1011 1100 1101 1110 1111 000 001 010 011 XIP enabling NVCR<11:9> at POR 100 101 110 111 ...
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... The default values of these bits allow the memory to be safely used with fast read instructions at the maximum frequency (108 MHz). Please note that if the dummy clock number is not sufficient for the operating frequency, the memory reads wrong data ...
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... The Quad Input NV configuration bit can be used to make the memory start working in QIO- SPI protocol directly after the power on sequence. The products are delivered with this set to 1, making the memory default in Extended SPI protocol, if the application sets this bit to 0 the device will enter in QIO-SPI protocol right after the next power on. ...
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... The Dual Input NV configuration bit can be used to make the memory start working in DIO- SPI protocol directly after the power on sequence. The products are delivered with this set to 1, making the memory default in Extended SPI protocol, if the application sets this bit to 0 the device will enter in QIO-SPI protocol right after the next power on. ...
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... Note: If the dummy clock number is not sufficient for the operating frequency, the memory reads wrong data. 40/185 Value Description ...
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... The bit 3 of the Volatile Configuration Register is the XIP enabling bit, this bit must be set enable the memory working on XIP mode. For devices with a feature set digit equal the part number (Basic XiP), this bit is always Don't Care, and it is possible to operate the memory in XIP mode without setting ...
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... QIO-SPI protocol directly after the Write Volatile Enhanced Configuration Register (WRVECR) instruction. The default value of this bit is 1, corresponding to Extended SPI protocol, If this bit is set to 0 the memory works in QIO-SPI protocol. If VECR bit 7 is set back to 1 the memory start working again in Extended SPI protocol, unless the bit 6 is set to 0 (in this case the memory start working in DIO-SPI mode) ...
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... If the Volatile Enhanced Configuration Register bit 3 is set to 0, after any quad modify instruction (both in Extended SPI protocol and QIO-SPI protocol), there is a maximum allowed time-out of 200 ms after the last instruction input is received and the memory is de- selected to raise the Vpp signal to Vpph; otherwise, the modify instruction starts at normal speed, without the Vpph enhancement, and a flag error appears on Flag Status Register bit 3 ...
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... Erase Suspend bit and Program Suspend bit) are a “Status Indicator bit”, they are set and reset automatically by the memory. Four bits (Erase error bit, Program error bit, VPP error bit and Protection error bit) are “Error Indicators bits”, they are set by the memory when some program or erase operation fails or the user tries to perform a forbidden operation ...
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Table 8. Flag Status Register BIT 7 P/E Controller (not WIP) 6 Erase Suspend 5 Erase 4 Program 3 VPP 2 Program Suspend 1 Protection 0 RESERVED 6.5.1 P/E Controller Status bit The bit 7 of the Flag Status register ...
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The Erase Status bit is related to all possible erase operations: Sector Erase, Sub Sector Erase, and Bulk Erase in all the three available protocols (SPI, DIO-SPI and QIO-SPI). Once the bit 5 is set High, it can only be ...
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The bit is set (FSR<2>=1) within the Erase Suspend Latency time, that is as soon as the Program/Erase Suspend command (PES) has been issued, therefore the device may still complete the operation before entering the Suspend Mode. The Program Suspend ...
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... Specific hardware and software protection There are two software protected modes, SPM1 and SPM2, that can be combined to protect the memory array as required. The SPM2 can be locked by hardware with the help of the W input pin. SPM1 The first software protected mode (SPM1) is managed by specific Lock Registers assigned to each 64 Kbyte sector ...
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... The definition of the Lock Register bits is given in Table 9: Lock Register out. SPM2 The second software protected mode (SPM2) uses the Block Protect bits (BP3, BP2, BP1, BP0) and the Top/Bottom bit (TB bit) to allow part of the memory to be configured as read- only. See Section 16: Ordering Table 9 ...
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... Memory Content Protected Area 0 None Upper 256th 1 (1/2 Mbit, sector 255) Upper 128th 0 (1 Mbit, 2 sectors: 254 to 255) Upper 64th 1 (2 Mbit, 4 sectors: 252 to 255) Upper 32nd 0 (4 Mbit, 8 sectors: 248 to 255) Upper 16th 1 (8 Mbit, 16 sectors: 240 to 255) Upper 8th ...
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... The N25Q128 is available in the following architecture versions: Bottom version uniform sectors plus 8 bottom boot sectors (each with 16 subsectors), Top version uniform sectors plus 8 top boot sectors (each with 16 subsectors) Uniform version uniform sectors without any boot sectors and subsectors. Memory Content Protected Area 0 None Lower 256th ...
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... Kbytes) and 248 standard 64 KB sectors 65,536 pages (256 bytes each) 64 OTP bytes located outside the main memory array Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from but not Page Erasable, Subsector Erase is allowed on the 8 boot sectors (for devices with bottom or top architecture) ...
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... Table 12. Memory organization (uniform) (page Sector Address range 255 FF0000 FFFFFF 254 FE0000 FEFFFF 253 FD0000 FDFFFF 252 FC0000 FCFFFF 251 FB0000 FBFFFF 250 FA0000 FAFFFF 249 F90000 F9FFFF 248 F80000 F8FFFF 247 F70000 F7FFFF 246 F60000 F6FFFF 245 F50000 F5FFFF ...
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... Table 12. Memory organization (uniform) (page Sector 221 DD0000 220 DC0000 219 DB0000 218 DA0000 217 D90000 216 D80000 215 D70000 214 D60000 213 D50000 212 D40000 211 D30000 210 D20000 209 D10000 208 D00000 207 CF0000 206 CE0000 205 CD0000 204 ...
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... Table 12. Memory organization (uniform) (page Sector Address range 186 BA0000 BAFFFF 185 B90000 B9FFFF 184 B80000 B8FFFF 183 B70000 B7FFFF 182 B60000 B6FFFF 181 B50000 B5FFFF 180 B40000 B4FFFF 179 B30000 B3FFFF 178 B20000 B2FFFF 177 B10000 B1FFFF 176 B00000 B0FFFF ...
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... Table 12. Memory organization (uniform) (page Sector 151 970000 150 960000 149 950000 148 940000 147 930000 146 920000 145 910000 144 900000 143 8F0000 142 8E0000 141 8D0000 140 8C0000 139 8B0000 138 8A0000 137 890000 136 880000 135 870000 134 ...
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... Table 12. Memory organization (uniform) (page Sector Address range 116 740000 74FFFF 115 730000 73FFFF 114 720000 72FFFF 113 710000 71FFFF 112 700000 70FFFF 111 6F0000 6FFFFF 110 6E0000 6EFFFF 109 6D0000 6DFFFF 108 6C0000 6CFFFF 107 6B0000 6BFFFF 106 6A0000 6AFFFF ...
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... Table 12. Memory organization (uniform) (page Sector 81 510000 80 500000 79 4F0000 78 4E0000 77 4D0000 76 4C0000 75 4B0000 74 4A0000 73 490000 72 480000 71 470000 70 460000 69 450000 68 440000 67 430000 66 420000 65 410000 64 400000 63 3F0000 62 3E0000 61 3D0000 60 3C0000 59 3B0000 58 3A0000 57 390000 56 380000 55 370000 54 360000 53 350000 52 340000 51 330000 50 320000 49 310000 48 300000 47 2F0000 ...
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... Table 12. Memory organization (uniform) (page Sector Address range 46 2E0000 2EFFFF 45 2D0000 2DFFFF 44 2C0000 2CFFFF 43 2B0000 2BFFFF 42 2A0000 2AFFFF 41 290000 29FFFF 40 280000 28FFFF 39 270000 27FFFF 38 260000 26FFFF 37 250000 25FFFF 36 240000 24FFFF 35 230000 23FFFF 34 220000 22FFFF 33 210000 21FFFF 32 200000 20FFFF 31 1F0000 1FFFFF 30 1E0000 ...
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... Table 12. Memory organization (uniform) (page Sector 11 B0000 10 A0000 9 90000 8 80000 7 70000 6 60000 5 50000 4 40000 3 30000 2 20000 1 10000 0 0 Table 13. Memory organization (bottom) (page Sector Subsector 255 - 254 - 253 - 252 - 251 - 250 - 249 - 248 - 247 - 246 - 245 - 244 - 243 - 242 - 241 - 240 ...
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... Table 13. Memory organization (bottom) (page Sector Subsector 235 - EB0000 234 - EA0000 233 - E90000 232 - E80000 231 - E70000 230 - E60000 229 - E50000 228 - E40000 227 - E30000 226 - E20000 225 - E10000 224 - E00000 223 - DF0000 222 - DE0000 221 - DD0000 220 - DC0000 219 - DB0000 ...
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... Table 13. Memory organization (bottom) (page Sector Subsector 200 - 199 - 198 - 197 - 196 - 195 - 194 - 193 - 192 - 191 - 190 - 189 - 188 - 187 - 186 - 185 - 184 - 183 - 182 - 181 - 180 - 179 - 178 - 177 - 176 - 175 - 174 - 173 - 172 - 171 - 170 - 169 - 168 - 167 ...
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... Table 13. Memory organization (bottom) (page Sector Subsector 165 - A50000 164 - A40000 163 - A30000 162 - A20000 161 - A10000 160 - A00000 159 - 9F0000 158 - 9E0000 157 - 9D0000 156 - 9C0000 155 - 9B0000 154 - 9A0000 153 - 990000 152 - 980000 151 - 970000 150 - 960000 149 - 950000 ...
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... Table 13. Memory organization (bottom) (page Sector Subsector 130 - 129 - 128 - 127 - 126 - 125 - 124 - 123 - 122 - 121 - 120 - 119 - 118 - 117 - 116 - 115 - 114 - 113 - 112 - 111 - 110 - 109 - 108 - 107 - 106 - 105 - 104 - 103 - 102 - 101 - 100 - 64/185 Address range ...
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... Table 13. Memory organization (bottom) (page Sector Subsector 95 - 5F0000 94 - 5E0000 93 - 5D0000 92 - 5C0000 91 - 5B0000 90 - 5A0000 89 - 590000 88 - 580000 87 - 570000 86 - 560000 85 - 550000 84 - 540000 83 - 530000 82 - 520000 81 - 510000 80 - 500000 79 - 4F0000 78 - 4E0000 77 - 4D0000 76 - 4C0000 75 - 4B0000 74 - 4A0000 73 - 490000 72 - 480000 71 - 470000 70 - 460000 69 - 450000 68 - 440000 67 - 430000 66 - 420000 65 - 410000 64 - 400000 63 - 3F0000 62 - 3E0000 ...
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... Table 13. Memory organization (bottom) (page Sector Subsector 66/185 Address range 3C0000 3CFFFF 3B0000 3BFFFF 3A0000 3AFFFF 390000 39FFFF 380000 38FFFF 370000 37FFFF 360000 36FFFF 350000 35FFFF 340000 34FFFF 330000 33FFFF 320000 32FFFF 310000 31FFFF 300000 30FFFF 2F0000 2FFFFF 2E0000 2EFFFF 2D0000 ...
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... Table 13. Memory organization (bottom) (page Sector Subsector 25 - 190000 24 - 180000 23 - 170000 22 - 160000 21 - 150000 20 - 140000 19 - 130000 18 - 120000 17 - 110000 16 - 100000 15 - F0000 14 - E0000 13 - D0000 12 - C0000 11 - B0000 10 - A0000 9 - 90000 8 - 80000 127 7F000 7 112 70000 111 6F000 6 96 60000 95 5F000 5 80 50000 79 4F000 4 64 40000 63 3F000 3 48 ...
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... Table 13. Memory organization (bottom) (page Sector Subsector Table 14. Memory organization (top) Sector Subsector 127 255 112 111 254 96 95 253 80 79 252 64 63 251 48 47 250 32 31 249 16 15 248 0 247 - 246 - 245 - 68/185 Address range 1F000 1FFFF 10000 10FFF F000 ...
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... Table 14. Memory organization (top) Sector Subsector 244 - F40000 243 - F30000 242 - F20000 241 - F10000 240 - F00000 239 - EF0000 238 - EE0000 237 - ED0000 236 - EC0000 235 - EB0000 234 - EA0000 233 - E90000 232 - E80000 231 - E70000 230 - E60000 229 - E50000 228 - E40000 227 ...
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... Table 14. Memory organization (top) Sector Subsector 209 - 208 - 207 - 206 - 205 - 204 - 203 - 202 - 201 - 200 - 199 - 198 - 197 - 196 - 195 - 194 - 193 - 192 - 191 - 190 - 189 - 188 - 187 - 186 - 185 - 184 - 183 - 182 - 181 - 180 - 179 - 178 - 177 - 176 - 175 ...
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... Table 14. Memory organization (top) Sector Subsector 174 - AE0000 173 - AD0000 172 - AC0000 171 - AB0000 170 - AA0000 169 - A90000 168 - A80000 167 - A70000 166 - A60000 165 - A50000 164 - A40000 163 - A30000 162 - A20000 161 - A10000 160 - A00000 159 - 9F0000 158 - 9E0000 157 ...
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... Table 14. Memory organization (top) Sector Subsector 139 - 138 - 137 - 136 - 135 - 134 - 133 - 132 - 131 - 130 - 129 - 128 - 127 - 126 - 125 - 124 - 123 - 122 - 121 - 120 - 119 - 118 - 117 - 116 - 115 - 114 - 113 - 112 - 111 - 110 - 109 - 108 - 107 - 106 - 105 ...
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... Table 14. Memory organization (top) Sector Subsector 104 - 680000 103 - 670000 102 - 660000 101 - 650000 100 - 640000 99 - 630000 98 - 620000 97 - 610000 96 - 600000 95 - 5F0000 94 - 5E0000 93 - 5D0000 92 - 5C0000 91 - 5B0000 90 - 5A0000 89 - 590000 88 - 580000 87 - 570000 86 - 560000 85 - 550000 84 - 540000 83 - 530000 82 - 520000 81 - 510000 80 - 500000 79 - 4F0000 78 - 4E0000 77 - 4D0000 76 - 4C0000 75 - 4B0000 ...
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... Table 14. Memory organization (top) Sector Subsector 74/185 Address range 450000 45FFFF 440000 44FFFF 430000 43FFFF 420000 42FFFF 410000 41FFFF 400000 40FFFF 3F0000 3FFFFF 3E0000 3EFFFF 3D0000 3DFFFF 3C0000 3CFFFF 3B0000 3BFFFF 3A0000 3AFFFF 390000 39FFFF 380000 38FFFF 370000 37FFFF 360000 36FFFF ...
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... Table 14. Memory organization (top) Sector Subsector 34 - 220000 33 - 210000 32 - 200000 31 - 1F0000 30 - 1E0000 29 - 1D0000 28 - 1C0000 27 - 1B0000 26 - 1A0000 25 - 190000 24 - 180000 23 - 170000 22 - 160000 21 - 150000 20 - 140000 19 - 130000 18 - 120000 17 - 110000 16 - 100000 15 - F0000 14 - E0000 13 - D0000 12 - C0000 11 - B0000 10 - A0000 9 - 90000 8 - 80000 7 - 70000 6 - 60000 5 - 50000 4 - 40000 3 - 30000 2 - 20000 1 - 10000 Address range ...
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... Depending on the instruction, this might be followed by address bytes data bytes both or none. In XIP modes only read operation and exit XIP mode can be performed, and to read the memory content no instructions code are needed: the device directly receives addresses and after a configurable number of dummy clock cycle it outputs the required data. 9.1 ...
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... That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array are ignored during: – Write Status Register cycle – ...
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Table 15. Instruction set: extended SPI protocol (page Instruction Description RDID Read Identification READ Read Data Bytes FAST_READ Read Data Bytes at Higher Speed DOFR Dual Output Fast Read DIOFR Dual Input/Output Fast Read QOFR Quad Output ...
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... The manufacturer identification is assigned by JEDEC, and has the value 20h. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (BBh), and the memory capacity of the device in the second byte (18h). The UID is composed by 17 read only bytes, containing the length of the following data in the first byte ...
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... Serial Clock (C). The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely ...
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... Serial Clock (C). The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction ...
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... The device is first selected by driving Chip Select (S) Low. The instruction code for the Dual Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, are shifted out on DQ0 and DQ1 at a maximum frequency Fc, during the falling edge of Serial Clock (C) ...
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Figure 13. Dual Output Fast Read instruction sequence S Mode Mode 2 Instruction DQ0 DQ1 Dummy cycles DQ0 ...
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... The device is first selected by driving Chip Select (S) Low. The instruction code for the Quad Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, are shifted out on pin DQ0, pin DQ1, pin W/VPP/DQ2 and pin HOLD/DQ3 ( maximum frequency fC, during the falling edge of Serial Clock (C) ...
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Note: Reset functionality is available instead of Hold in devices with a dedicated part number. See Section 16: Ordering Figure 15. Quad Input/Output Fast Read instruction sequence S Mode Mode 0 Instruction DQ0 ...
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... OTP (ROTP) instruction is followed by a 3-byte address (A23- A0) and a dummy byte. Each bit is latched in on the rising edge of Serial Clock (C). Then the memory contents at that address are shifted out on Serial Data output (DQ1). Each bit is shifted out at the maximum frequency, fCmax, on the falling edge of Serial Clock (C) ...
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Figure 17. Read OTP instruction and data-out sequence Instruction DQ0 High Impedance DQ1 Dummy cycles 7 ...
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WIP bit of the Status Register or of the Program/Erase controller bit of the Flag Status register): to verify if the POR sequence is completed is ...
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... DQ1 9.1.11 Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...
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Chip Select (S) must be driven Low for the entire duration of the sequence. If more than 256 bytes are sent to the device, previously latched ...
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Figure 20. Page Program instruction sequence Instruction DQ0 Data byte DQ0 MSB ...
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Dual Input Fast Program (DIFP) sequences each containing only a few bytes. See Table 33.: AC Characteristics. Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the ...
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Dual Input Extended Fast Program The Dual Input Extended Fast Program (DIEFP) instruction is very similar to the Dual Input Fast Program (DIFP), except that the address bits are shifted in on two pins (pin DQ0 and pin DQ1) ...
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If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to ...
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... Bit 0 of the OTP control byte, that is byte 64, is used to permanently lock the OTP memory array. When bit 0 of byte 64 = '1', the 64 bytes of the OTP memory array can be programmed. When bit 0 of byte 64 = '0', the 64 bytes of the OTP memory array are read-only and cannot be programmed anymore. 5 ...
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... Once a bit of the OTP memory has been programmed to '0', it can no longer be set to '1'. Therefore, as soon as bit 0 of byte 64 (control byte) is set to '0', the 64 bytes of the OTP memory array become read-only in a permanent way. Any Program OTP (POTP) instruction issued while an Erase, Program or Write cycle is in progress is rejected without having any effect on the cycle that is in progress ...
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Figure 26. How to permanently lock the OTP bytes Byte Byte Byte 9.1.17 Subsector Erase (SSE) For devices with bottom or top architecture, at the bottom (or top) of the addressable area there are 8 boot sectors, ...
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Figure 27. Subsector Erase instruction sequence DQ0 9.1.18 Sector Erase (SE) The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must ...
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Figure 28. Sector Erase instruction sequence S C DQ0 9.1.19 Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After ...
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Program/Erase Suspend The Program/Erase Suspend instruction allows the controller to interrupt a Program or an Erase instruction, in particular: Sector Erase, Subsector Erase, Page Program, Dual Input Page Program, Dual Input Extended Page program, Quad Input Page Program and ...
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Table 19. Operations Allowed / Disallowed During Device States Device States and Sector (Same/Other) in Which Operation is Allowed/Disallowed (Yes/No) Standby State Program State Operation Sector Same Other Same All Reads except RDSR / Yes Yes RDFSR Array Program: PP ...
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Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. ...
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... Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction (attempts to write to the Status Register are rejected, and are not accepted for execution consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, are also hardware protected against data modification ...
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... Write protection of the status register 24-bit address MSB Memory content (1) Protected area Unprotected area Protected against PP, Ready to accept PP, DIFP, DIEFP, QIFP, DIFP, DIEFP, QIFP, QIEFP, SSE, SE and QIEFP, SSE, and SE BE instructions. instructions. PP, DIFP, DIEFP, PP, DIFP, DIEFP, QIFP, QIEFP, SSE, QIFP, QIEFP, SSE, SE and BE and SE instructions ...
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... The Write Lock and Lock Down bits can be changed by writing new values to them. Write, Program and Erase operations in this sector will not be executed. The ‘1’ memory contents will not be changed. Sector b0 Write Lock Write, Program and Erase operations in this sector are executed and will modify the ‘ ...
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Table 22. Lock Register in Sector All sectors 1. Values of (b1, b0) after power-up are defined in 9.1.26 Read Flag Status Register The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be read. The Status ...
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Figure 35. Clear Flag Status Register instruction sequence S C DQ0 DQ1 9.1.28 Read NV Configuration Register The Read Non Volatile Configuration Register (RDNVCR) instruction allows the Non Volatile Configuration Register to be read. Figure 36. Read NV Configuration Register ...
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... The Write Non Volatile Configuration register (WRNVCR) instruction allows the user to change the values of all the Non Volatile Configuration Register bits, described in Non-Volatile Configuration The Write Non Volatile Configuration Register impacts the memory behavior only after the next power on sequence. Figure 37. Write NV Configuration Register instruction sequence ...
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... When the new data are latched, the write enable latch (WEL) is reset. The Write Volatile Configuration register (WRVCR) instruction allows the user to change the values of all the Volatile Configuration Register bits, described in Configuration Register. The Write Volatile Configuration Register impacts the memory behavior right after the instruction is received by the device ...
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Figure 39. Write Volatile Configuration Register instruction sequence DQ0 High Impedance DQ1 9.1.32 Read Volatile Enhanced Configuration Register The Read Volatile Enhanced Configuration Register (RDVECR) instruction allows the Volatile Configuration Register to be read. Figure 40. ...
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... The Write Volatile Enhanced Configuration register (WRVECR) instruction allows the user to change the values of all the Volatile Enhanced Configuration Register bits, described in Table 7.: Volatile Enhanced Configuration The Write Volatile Enhanced Configuration Register impacts the memory behavior right after the instruction is received by the device. Figure 41. Write Volatile Enhanced Configuration Register instruction sequence ...
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The Deep Power-down mode automatically stops at power-down, and the device always powers up in the Standby Power mode. The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data ...
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... High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. All attempts to access the memory array during a Write Status Register cycle, a Write Non Volatile Configuration Register, a Program cycle or an Erase cycle are ignored, and the internal Write Status Register cycle, Write Non Volatile Configuration Register, Program ...
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Table 23. Instruction set: DIO-SPI protocol Instruction Description MIORDID Multiple I/O read identification DCFR Dual Command Fast Read ROTP Read OTP WREN Write Enable WRDI Write Disable DCPP Dual Command Page Program POTP Program OTP (2) SSE SubSector Erase SE ...
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... The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code for the instruction is shifted in parallel on the 2 pins DQ0 and DQ1. After this, the 24-bit device identification, stored in the memory, will be shifted out on again in parallel on DQ1 and DQ0. Each two bits are shifted out during the falling edge of Serial Clock (C). ...
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... DQ1). The Dual Command Fast Read (DCFR) instruction can be issued, when the device is set in DIO-SPI mode, by sending to the memory indifferently one of the 3 instructions codes: 0Bh, 3Bh or BBh, the effect is exactly the same. The 3 instruction codes are all accepted to help the application code porting from Extended SPI protocol to DIO-SPI protocol ...
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Figure 46. Read OTP instruction and data-out sequence DIO-SPI Instruction 24-Bit Address DQ0 DQ1 ...
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... The Dual Command Page Program (DCPP) instruction can be issued, when the device is set in DIO-SPI mode, by sending to the memory indifferently one of the 3 instructions codes: 02h, A2h or D2h, the effect is exactly the same. The 3 instruction codes are all accepted to help the application code porting from Extended SPI protocol to DIO-SPI protocol ...
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... Program OTP instruction (POTP) The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP memory area (by changing bits from only). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. Apart form the parallelizing of the instruction code, address and input data on the two pins ...
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Figure 52. Program OTP instruction sequence DIO-SPI Instruction DQ0 DQ1 9.2.8 Subsector Erase (SSE) For devices with bottom or top architecture, at the bottom (or ...
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Sector Erase (SE) The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. Apart form the parallelizing of the ...
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Figure 55. Bulk Erase instruction sequence DIO-SPI S C DQ0 DQ1 9.2.11 Program/Erase Suspend The Program/Erase Suspend instruction allows the controller to interrupt a Program or an Erase instruction, in particular: Sector Erase and Dual Command Page Program can be ...
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Extended SPI protocol, please refer to Resume for further details. Figure 57. Program/Erase Resume instruction sequence DIO-SPI S C DQ0 DQ1 Section 9.1.21: Program/Erase Instruction Dual_Program_Erase_Resume 123/185 ...
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Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. Apart form the parallelizing of the instruction code and the output data on the two pins DQ0 and DQ1, the instruction functionality ...
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Read Lock Register (RDLR) The Read Lock Register instructions is used to read the lock register content. Apart form the parallelizing of the instruction code, the address and the output data on the two pins DQ0 and DQ1, the ...
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Figure 61. Write to Lock Register instruction sequence DIO-SPI Instruction DQ0 DQ1 9.2.17 Read Flag Status Register The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be read. Apart form the ...
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Clear Flag Status Register The Clear Flag Status Register (CLFSR) instruction reset the error Flag Status Register bits (Erase Error bit, Program Error bit, VPP Error bit, Protection Error bit not necessary to set the WEL bit ...
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Write NV Configuration Register The Write Non Volatile Configuration register (WRNVCR) instruction allows new values to be written to the Non Volatile Configuration register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. ...
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Figure 66. Read Volatile Configuration Register instruction sequence DIO-SPI S C DQ0 DQ1 9.2.22 Write Volatile Configuration Register The Write Volatile Configuration register (WRVCR) instruction allows new values to be written to the Volatile Configuration register. Before it can be ...
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Read Volatile Enhanced Configuration Register The Read Volatile Enhanced Configuration Register (RDVECR) instruction allows the Volatile Configuration Register to be read. Figure 68. Read Volatile Enhanced Configuration Register instruction sequence DIO-SPI S C DQ0 DQ1 9.2.24 Write Volatile Enhanced ...
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Figure 69. Write Volatile Enhanced Configuration Register instruction sequence DIO-SPI S C DQ0 DQ1 9.2.25 Deep Power-down (DP) The Deep-Power-down (DP) instruction sets the device in Deep Power-down mode. Apart form the parallelizing of the instruction code on the two ...
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Release from Deep Power-down (RDP) Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down (RDP) instruction. Executing this instruction takes the device out of the Deep Power-down mode. Apart ...
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... All attempts to access the memory array during a Write Status Register cycle, a Write Non Volatile Configuration Register, a Program cycle or an Erase cycle are ignored, and the internal Write Status Register cycle, Write Non Volatile Configuration Register, Program cycle or Erase cycle continues unaffected, the only exception is the Program/Erase Suspend instruction (PES), that can be used to pause all the program and the erase cycles but the Program OTP (POT), Bulk Erase (BE) and Write Non Volatile Configuration Register ...
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... DQ0, DQ1, DQ2 and DQ3. After this, the 24-bit device identification, stored in the memory, will be shifted out on again in parallel on DQ0, DQ1, DQ2 and DQ3. The identification bits are shifted out time during the falling edge of Serial Clock (C) ...
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... DQ1, DQ2 and DQ3). The Quad Command Fast Read (QCFR) instruction can be issued, after the device is set in QIO-SPI mode, by sending to the memory indifferently one of the 3 instructions codes: 0Bh, 6Bh or EBh, the effect is exactly the same. The 3 instruction codes are all accepted to help the application code porting from Extended SPI protocol to QIO-SPI protocol ...
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Figure 73. Quad Command Fast Read instruction and data-out sequence QSP, 0Bh S Mode Mode 0 Instruction 4 0 DQ0 DQ1 5 1 DQ2 6 2 DQ3 7 3 A23-16 A15-8 A7-0 Figure 74. ...
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Figure 75. Quad Command Fast Read instruction and data-out sequence QSP, EBh S Mode Mode 0 Instruction 4 0 DQ0 DQ1 5 1 DQ2 6 2 DQ3 7 3 A23-16 A15-8 A7-0 9.3.3 Read ...
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Figure 76. Read OTP instruction and data-out sequence QIO-SPI Instruction DQ0 DQ1 DQ2 DQ3 9.3.4 Write Enable (WREN) The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit. Apart form the parallelizing of the ...
Page 139
... The Quad Command Page Program (QCPP) instruction can be issued, when the device is set in QIO-SPI mode, by sending to the memory indifferently one of the 3 instructions codes: 02h, 12h or 32h, the effect is exactly the same. The 3 instruction codes are all accepted to help the application code porting from Extended SPI protocol to QIO-SPI protocol ...
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Figure 79. Quad Command Page Program instruction sequence QIO-SPI, 02h S Mode Mode 0 24-bit address DQ0 DQ1 DQ2 ...
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... Program OTP instruction (POTP) The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP memory area (by changing bits from only). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. Apart form the parallelizing of the instruction code, address and input data on the four pins ...
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Figure 82. Program OTP instruction sequence QIO-SPI Instruction DQ0 DQ1 DQ2 DQ3 9.3.8 Subsector Erase (SSE) For devices with a dedicated part number, at the bottom (or top) of the addressable area there are 8 boot sectors, ...
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Figure 83. Subsector Erase instruction sequence QIO-SPI S C DQ0 DQ1 DQ2 DQ3 9.3.9 Sector Erase (SE) The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable ...
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Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. Apart form the parallelizing of the instruction code on the ...
Page 145
Figure 86. Program/Erase Suspend instruction sequence QIO-SPI DQ0 DQ1 DQ2 DQ3 9.3.12 Program/Erase Resume After a Program/Erase suspend instruction, a Program/Erase Resume instruction is required to continue performing the suspended Program or Erase sequence. Apart form the parallelizing of the ...
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Figure 87. Program/Erase Resume instruction sequence QIO-SPI DQ0 DQ1 DQ2 DQ3 9.3.13 Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. Apart form the parallelizing of the instruction code and the output ...
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Figure 88. Read Status Register instruction sequence QIO-SPI Instruction DQ0 DQ1 DQ2 DQ3 9.3.14 Write status register (WRSR) The write status register (WRSR) instruction allows new values to be written to the status register. Before it ...
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Figure 89. Write Status Register instruction sequence QIO-SPI S C DQ0 DQ1 DQ2 DQ3 9.3.15 Read Lock Register (RDLR) The Read Lock Register instructions is used to read the lock register content. Apart form the parallelizing of the instruction code, ...
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Figure 90. Read Lock Register instruction and data-out sequence QIO-SPI Instruction DQ0 DQ1 DQ2 DQ3 9.3.16 Write to Lock Register (WRLR) The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock ...
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Figure 91. Write to Lock Register instruction sequence QIO-SPI S C DQ0 DQ1 DQ2 DQ3 9.3.17 Read Flag Status Register The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be read. Apart form the parallelizing of ...
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Figure 92. Read Flag Status Register instruction sequence QIO-SPI S Mode Mode 0 Instruction DQ0 DQ1 DQ2 DQ3 9.3.18 Clear Flag Status Register The Clear Flag Status Register (CLFSR) instruction reset the error Flag Status Register bits ...
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Figure 93. Clear Flag Status Register instruction sequence QIO-SPI 9.3.19 Read NV Configuration Register The Read Non Volatile Configuration Register (RDNVCR) instruction allows the Non Volatile Configuration Register to be read. 152/185 Instruction DQ0 DQ1 DQ2 ...
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Figure 94. Read NV Configuration Register instruction sequence QIO-SPI S C DQ0 DQ1 DQ2 DQ3 9.3.20 Write NV Configuration Register The Write Non Volatile Configuration register (WRNVCR) instruction allows new values to be written to the Non Volatile Configuration register. ...
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Figure 95. Write NV Configuration Register instruction sequence QIO-SPI S C DQ0 DQ1 DQ2 DQ3 9.3.21 Read Volatile Configuration Register The Read Volatile Configuration Register (RDVCR) instruction allows the Volatile Configuration Register to be read. 154/185 ...
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Figure 96. Read Volatile Configuration Register instruction sequence QIO-SPI Instruction DQ0 DQ1 DQ2 DQ3 9.3.22 Write Volatile Configuration Register The Write Volatile Configuration register (WRVCR) instruction allows new values to be written to the Volatile Configuration ...
Page 156
Figure 97. Write Volatile Configuration Register instruction sequence QIO-SPI S C DQ0 DQ1 DQ2 DQ3 9.3.23 Read Volatile Enhanced Configuration Register The Read Volatile Enhanced Configuration Register (RDVECR) instruction allows the Volatile Configuration Register to be read. 156/185 0 1 ...
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Figure 98. Read Volatile Enhanced Configuration Register instruction sequence QIO-SPI Instruction DQ0 DQ1 DQ2 DQ3 9.3.24 Write Volatile Enhanced Configuration Register The Write Volatile Enhanced Configuration register (WRVECR) instruction allows new values to be written to the ...
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Figure 99. Write Volatile Enhanced Configuration Register instruction sequence QIO-SPI S C DQ0 DQ1 DQ2 DQ3 158/185 Volatile Enhanced Configuration Register In Instruction Quad_Write_VECR ...
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Deep Power-down (DP) The Deep-Power-down (DP) instruction sets the device in Deep Power-down mode. Apart form the parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as ...
Page 160
Release from Deep Power-down (RDP) Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down (RDP) instruction. Executing this instruction takes the device out of the Deep Power-down mode. Apart ...
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... While acting on the Non Volatile Configuration Register (bit 11 to bit 9, depending on which XIP type is required, single, dual or quad I/O) the memory enters in the selected XIP mode only after the next power-on sequence. The Non Volatile Configuration Register XIP configuration bits allows the memory to start directly in the required XIP mode (Single, Dual or Quad) after the power on ...
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... Register (WRNVCR) instruction. (See This instruction doesn't affect the XIP state until the next Power on sequence. In this case, after the next power on sequence, the memory directly accept addresses and then, after the dummy clock cycles (configurable), outputs the data as described in bits setting example ...
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Table 25. NVCR XIP bits setting example B1h (WRNVCR + 0110 opcode) 6 dummy cycles for fast read instructions XIP set as default; Quad I/O mode Figure 103. XIP mode directly after power on NVCR check: XIP enabled Vd t ...
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... DQ0 during the first dummy cycle after the address has been received), Then after the next de-select and select cycle (S pin set to 1 and then to 0) the memory codify the first 3 bytes received on the input pin(s) directly as an address, without any instruction code, and after the dummy clock cycles (configurable) directly outputs the data ...
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... XIP mode hold and exit The XIP mode does require at least one additional clock cycle to allow the XIP Confirmation bit to be sent to the memory on DQ0 during the first dummy clock cycle. The device decodes the XIP Confirmation bit with the scheme: ...
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... POR state and there is no issue. See In all the other cases possible to exit the memory from the XIP mode by sending the following rescue sequence at the first chip selection after a system reset: ...
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Power-up and power-down At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on VCC) until VCC reaches the correct value: VCC(min) at power-up, and then for a further ...
Page 168
Figure 105. Power-up timing, Fast POR selected Vcc V (max) CC Chip selection not allowed V (min) CC Chip reset V WI Figure 106. Power-up timing, Fast POR not selected Vcc V (max) CC Chip selection not allowed V (min) ...
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... Fast POR The Fast POR feature is available to speed up the power-on sequence for applications that only require reading the memory after the power on sequence (no modify instructions). If enabled, the Fast POR allows read operations and Volatile Configuration Register and Volatile Enhanced Configuration Register modifications after less than 100us, providing a substantially faster application boot phase ...
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... Fast program/erase voltage V Electrostatic discharge voltage (human body model) ESD 1. Compliant with JEDEC Std. J-STD-020C (for small body, Sn- assembly), the Numonyx ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. Avoid applying VPP 3. JEDEC Std JESD22-A114A (C1 = 100 pF 1500 Ω 500 Ω). ...
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DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow are derived from tests performed under the ...
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Table 32. DC Characteristics Symbol Parameter ILI Input leakage current ILO Output leakage current ICC1 Standby current ICC2 Deep Power-down current Operating current (Fast Read Single I/O) ICC3 Operating current (Fast Read Dual I/O) Operating current (Fast Read Quad I/O) ...
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Note: The AC Characteristics data is preliminary. Table 33. AC Characteristics (page Symbol Alt. Clock frequency for the all the fC fC instructions (Extended SPI, DIO-SPI and QIO-SPI protocol) but the READ instruction fR Clock frequency for ...
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Table 33. AC Characteristics (page Symbol Alt. Enhanced program supply voltage High (6) tVPPHSL (VPPH) to Chip Select Low for Single and Dual I/O Page Program tW Write status register cycle time tCFSR Clear flag status register ...
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Table 34. Reset Conditions Symbol Alt. Parameter (1)(2) tRLRH tRST Reset pulse width Reset Recovery (1) tRHSL tREC Time S# deselect to R (1) tSHRV valid tDP tRDP 1. All values are guaranteed by characterization and not 100% tested in ...
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Figure 110. Write protect setup and hold timing during WRSR when SRWD=1 W/V PP tWHSL S C DQ0 DQ1 Figure 111. Hold timing S C DQ1 DQ0 HOLD 176/185 High Impedance tHLCH tCHHL tCHHH tHLQZ tSHWL AI07439c tHHCH tHHQX AI13746 ...
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Figure 112. Output timing S C tCLQV tCLQX tCLQX DQ1 ADDR. DQ0 LSB IN Figure 113. VPP timing DQ0 V PPH V PP tVPPHSL tCH tCLQV tCL End of command (identified by WIP polling) tSHQZ LSB OUT ...
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... Package mechanical In order to meet environmental requirements, Numonyx offers these devices in RoHS compliant packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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Figure 115. SO16 wide - 16-lead plastic small outline, 300 mils body width, package outline SO-H 1. Drawing is not to scale. Table 36. SO16 wide - 16-lead plastic small outline, 300 mils body width, ...
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Figure 116. TBGA - mm, 24-ball, mechanical package outline 1. Drawing is not to scale. 180/185 ...
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Table 37. TBGA 6x8 mm 24-ball package dimensions MIN A A1 0.20 A2 0.79 Øb 0.35 0.40 D 5.90 6.00 D1 4.00 E 7.90 8.00 E1 4.00 eD 1.00 eE 1.00 FD 1. ...
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... Device density 128 = 128 Mbit Technology Feature set 1 = Byte addressability, Hold pin, Numonyx XiP 2 = Byte addressability, Hold pin, Basic XiP 3 = Byte addressability, Reset pin, Numonyx XiP 4 = Byte addressability, Reset pin, Basic XiP Operating voltage 1 = VCC = 1 Block Structure B = Bottom T = Top E = Uniform (no boot sectors) ...
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... N25Q128A11T1240E Byte addressability, Hold pin, Numonyx XiP N25Q128A11T1240F N25Q128A21T1240E Byte addressability, Hold pin, Basic XiP N25Q128A21T1240F N25Q128A11BSF40F Byte addressability, Hold pin, Numonyx XiP N25Q128A11BSF40G N25Q128A21BSF40F Byte addressability, Hold pin, Basic XiP N25Q128A21BSF40G N25Q128A11TSF40F Byte addressability, Hold pin, Numonyx XiP N25Q128A11TSF40G N25Q128A21TSF40F ...
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Revision history Table 40. Document revision history Date Revision 12-Feb-2010 1.0 184/185 Changes Initial public release. ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...