PSD813F2A-90MI STMicroelectronics, PSD813F2A-90MI Datasheet - Page 12
![IC FLASH 1MBIT 90NS 52QFP](/photos/7/25/72513/497-52-pqfp_series_sml.jpg)
PSD813F2A-90MI
Manufacturer Part Number
PSD813F2A-90MI
Description
IC FLASH 1MBIT 90NS 52QFP
Manufacturer
STMicroelectronics
Datasheet
1.PSD813F2VA-20JI.pdf
(109 pages)
Specifications of PSD813F2A-90MI
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
1M (128K x 8)
Speed
90ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
52-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-1991
Available stocks
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Manufacturer
Quantity
Price
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MICROCHIP
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PSD813F2V, PSD854F2V
12/109
Pin Name
PC2
PC3
PC4
PC5
PC6
Pin
18
17
14
13
12
Type
I/O
I/O
I/O
I/O
I/O
PC2 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC2) output.
Input to the PLDs.
This pin can be configured as a CMOS or Open Drain output.
PC3 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC3) output.
Input to the PLDs.
TSTAT output
Ready/Busy output for parallel In-System Programming (ISP).
This pin can be configured as a CMOS or Open Drain output.
PC4 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC4) output.
Input to the PLDs.
TERR output
This pin can be configured as a CMOS or Open Drain output.
PC5 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC5) output.
Input to the PLDs.
TDI input
This pin can be configured as a CMOS or Open Drain output.
PC6 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC6) output.
Input to the PLDs.
TDO output
This pin can be configured as a CMOS or Open Drain output.
2
for the JTAG Serial Interface.
2
2
for the JTAG Serial Interface.
2
for the JTAG Serial Interface.
for the JTAG Serial Interface.
Doc ID 10552 Rev 3
Description