PSD813F2 STMicroelectronics, PSD813F2 Datasheet
PSD813F2
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PSD813F2 Summary of contents
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... PROGRAMMABLE POWER MANAGEMENT June 2004 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD813F2, PSD833F2 PSD834F2, PSD853F2, PSD854F2 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V Figure 1. Packages HIGH ENDURANCE: – ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PSD ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Memory Page Register PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 MCU Bus Interface JTAG Port In-System Programming (ISP Power Management Unit (PMU DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PSD Register Description and Address Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DETAILED OPERATION ...
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... PSD Interface to a Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 PSD Interface to a Non-Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Data Byte Enable Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 MCU Bus Interface Examples 80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 General Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Address Out Mode Address In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 3/110 ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Data Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Peripheral I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 JTAG In-System Programming (ISP Port Configuration Registers (PCR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Drive Select Register Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Data In Data Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 OMC Mask Register Input Macrocells (IMC Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Ports A and B – ...
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... PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 APPENDIX A.PQFP52 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 APPENDIX B.PLCC52 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 APPENDIX C.TQFP64 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 REVISION HISTORY 109 PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 5/110 ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 SUMMARY DESCRIPTION The PSD8XXFX family of memory systems for mi- crocontrollers (MCUs) brings In-System-Program- mability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications ...
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... Figure 2. PQFP52 Connections PD2 1 PD1 2 PD0 3 PC7 4 PC6 5 PC5 6 PC4 GND 9 PC3 10 PC2 11 PC1 12 PC0 13 PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 39 AD15 38 AD14 37 AD13 36 AD12 35 AD11 34 AD10 33 AD9 32 AD8 AD7 29 AD6 28 AD5 27 AD4 AI02858 7/110 ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Figure 3. PLCC52 Connections 8 PD2 9 PD1 10 PD0 11 PC7 12 PC6 13 PC5 14 PC4 GND 17 PC3 18 PC2 19 PC1 20 PC0 8/110 AD15 46 AD14 45 AD13 44 AD12 43 AD11 42 AD10 41 AD9 40 AD8 AD7 37 AD6 36 35 AD5 AD4 34 AI02857 ...
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... PD1 2 PD0 3 PC7 4 PC6 5 PC5 GND 10 GND 11 PC3 12 PC2 13 PC1 14 PC0 PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 48 CNTL0 47 AD15 46 AD14 45 AD13 44 AD12 43 AD11 42 AD10 41 AD9 40 AD8 AD7 36 AD6 35 AD5 34 AD4 33 AD3 AI09645 9/110 ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 PIN DESCRIPTION Table 2. Pin Description (for the PLCC52 package - Note 1) Pin Name Pin Type This is the lower Address/Data port. Connect your MCU address or address/data bus according to the following rules: If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect AD0-AD7 to this port ...
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... MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC1) output. PC1 19 I/O Input to the PLDs. TCK Input This pin can be configured as a CMOS or Open Drain output. PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Description 2 for the JTAG Serial Interface. 2 for the JTAG Serial Interface. 11/110 ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Pin Name Pin Type PC2 pin of Port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC2) output. PC2 18 I/O Input to the PLDs. V – SRAM stand-by voltage input for SRAM battery backup. ...
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... Note: 1. The pin numbers in this table are for the PLCC package only. See the package information from pin numbers on other package types. 2. These functions can be multiplexed with other functions. PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Description Table 74., page 102 onwards, for 13/110 ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Figure 5. PSD Block Diagram 14/110 AI02861E ...
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... The functional partitioning of the PLDs reduces power consumption, optimizes cost/performance, and eases design entry. PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 The DPLD is used to decode addresses and to generate Sector Select signals for the PSD inter- nal memory and registers. The DPLD has combi- natorial outputs ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 JTAG Port In-System Programming (ISP) can be performed through the JTAG signals on Port C. This serial in- terface allows complete programming of the entire PSD device. A blank device can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can be multiplexed with other functions on Port C ...
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... AND MEMORY MAPPING PSD Simulator PSDsilos III DEVICE SIMULATION (OPTIONAL) PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 PSDsoft Express directly supports two low cost device programmers form ST: PSDpro and FlashLINK (JTAG). Both of these programmers may be purchased through your local distributor/ representative, or directly from our web site using a credit card ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 PSD REGISTER DESCRIPTION AND ADDRESS OFFSET Table 6 shows the offset addresses to the PSD registers relative to the CSIOP base address. The CSIOP space is the 256 bytes of address that is al- located by the user to the internal PSD registers. Table 6. I/O Port Latched Address Output Assignments (Note1) ...
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... Total 512K PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Memory Blocks The PSD has the following memory blocks: – Primary Flash memory – Optional Secondary Flash memory – Optional SRAM The Memory Select signals for these blocks origi- nate from the Decode PLD (DPLD) and are user- defined in PSDsoft Express ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Primary Flash Memory and Secondary Flash memory Description The primary Flash memory is divided evenly into eight equal sectors. The secondary Flash memory is divided into four equal sectors. Each sector of either memory block can be separately protected from Program and Erase cycles. ...
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... The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the Sector Protection Status of the primary Flash memory. PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Cycle 2 Cycle 3 ...
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... During the READ operation, ad- dress bits A6, A1, and A0 must be '0,0,1,' respectively, and the appropriate Sector Select (FS0-FS7) must be High. The identifier for the PSD813F2/3/4/5 is E4h, and for the PSD83xF2 or PSD85xF2 it is E7h. Read Memory Sector Protection Status The primary Flash memory Sector Protection Sta- ...
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... Note Not guaranteed value, can be read either '1' or ’0.’ 2. DQ7-DQ0 represent the Data Bus bits, D7-D0. 3. FS0-FS7 and CSBOOT0-CSBOOT3 are active High. PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 For Flash memory, the MCU can perform a READ operation to obtain these status bits while an Erase or Program instruction is being executed by the embedded algorithm ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Data Polling Flag (DQ7) When erasing or programming in Flash memory, the Data Polling Flag Bit (DQ7) outputs the com- plement of the bit being entered for programming/ writing on the DQ7 Bit. Once the Program instruc- tion or the WRITE operation is completed, the true logic value is read on the Data Polling Flag Bit (DQ7 READ operation) ...
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... It is suggested (as with all Flash memories) to read the location again after the embedded program- PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 ming algorithm has completed, to compare the byte that was written to the Flash memory with the byte that was intended to be written. ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Data Toggle Checking the Toggle Flag Bit (DQ6 method of determining whether a Program or Erase cycle is in progress or has completed. Figure Data Toggle algorithm. When the MCU issues a Program instruction, the embedded algorithm within the PSD begins. The MCU then reads the location of the byte to be pro- grammed in Flash memory to check status ...
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... Error Flag Bit (DQ5), the Toggle Flag Bit (DQ6), and the Data Polling Flag Bit (DQ7), as detailed in the section entitled GRAMMING FLASH MEMORY, page PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 During execution of the Erase cycle, the Flash memory accepts only Reset and Suspend Sector 21. ...
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... Security_Bit 0 = Security Bit in device has not been set Security Bit in device has been set. 28/110 On the PSD813F2/3/4/5, the Reset Flash instruc- tion puts the Flash memory back into normal READ Mode. It may take the Flash memory few milliseconds to complete the Reset cycle. ...
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... V or greater. If the supply voltage falls below the battery voltage, an internal power switch-over to the battery occurs. PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 PC4 can be configured as an output that indicates when power is being drawn from the external bat- tery. Battery-on Indicator (VBATON, PC4) is High ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 SECTOR SELECT AND SRAM SELECT Sector Select (FS0-FS7, CSBOOT0-CSBOOT3) and SRAM Select (RS0) are all outputs of the DPLD. They are setup by writing equations for them in PSDabel. The following rules apply to the equations for these signals: 1. Primary Flash memory and secondary Flash memory Sector Select signals must not be larger than the physical sector size ...
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... PIO mode used used Flash memory enable not not access Flash PIO mode used used memory PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Primary Secondary Flash Flash Memory Memory Primary RS0 Flash Memory CSBOOT0-3 FS0-FS7 ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 PAGE REGISTER The 8-bit Page Register increases the addressing capability of the MCU by a factor 256. The contents of the register can also be read by the MCU. The outputs of the Page Register (PGR0- PGR7) are inputs to the DPLD decoder and can be ...
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... See the section entitled MANAGEMENT, page 62 on how to set the Turbo Bit. PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Additionally, five bits are available in PMMR2 to block MCU control signals from entering the PLDs. This reduces power consumption and can be used only when these MCU control signals are not used in PLD logic equations ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Figure 13. PLD Diagram 34/110 PORTS I/O BUS INPUT PLD ...
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... 2:0 ] (ALE,CLKIN,CSI) PDN (APD OUTPUT) CNTRL [ 2 READ/WRITE CONTROL SIGNALS) RESET RD_BSY PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 1 internal SRAM Select (RS0) signal (two product terms) 1 internal CSIOP Select (PSD Configuration Register) signal 1 JTAG Select signal (enables JTAG on Port C) 2 internal Peripheral Select signals (Peripheral I/O mode) ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Complex PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift reg- isters, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate three External Chip Se- lect (ECS0-ECS2), routed to Port D ...
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... Port B5, C5 McellBC6 Port B6, C6 McellBC7 Port B7, C7 PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 trolled by the XOR gate. The Output Macrocell (OMC) can implement either sequential logic, us- ing the flip-flop element, or combinatorial logic. The multiplexer selects between the sequential or combinatorial logic outputs. The multiplexer output can drive a port pin and has a feedback path to the AND Array inputs ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Product Term Allocator The CPLD has a Product Term Allocator. The PS- Dabel compiler uses the Product Term Allocator to borrow and place product terms from one macro- cell to another. The following list summarizes how product terms are allocated: ...
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... Figure 16. CPLD Output Macrocell PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 ARRAY AND BUS INPUT PLD 39/110 ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Input Macrocells (IMC) The CPLD has 24 Input Macrocells (IMC), one for each pin on Ports A, B, and C. The architecture of the Input Macrocells (IMC) is shown in 17., page 41. The Input Macrocells (IMC) are indi- vidually configurable, and can be used as a latch, register pass incoming Port signals prior to driving them onto the PLD input bus ...
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... Figure 17. Input Macrocell PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 ARRAY AND BUS INPUT PLD 41/110 ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Figure 18. Handshaking Communication Using Input Macrocells 42/110 ...
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... Note: 1. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PC7, PD0, PA3-0) can be configured for other I/O func- tions. 2. ALE/AS input is optional for MCUs with a non-multiplexed bus PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 bus types and control signals, are shown in Table 16. The interface type is specified using the PSD- soft Express Configuration ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 PSD Interface to a Multiplexed 8-Bit Bus Figure 19 shows an example of a system using a MCU with an 8-bit multiplexed bus and a PSD. The ADIO port on the PSD is connected directly to the MCU address/data bus. Address Strobe (ALE/AS, PD0) latches the address signals internally. ...
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... MCU BHE ALE RESET PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 MCU Bus Interface Examples Figure 21 through connections between the PSD and some popular MCUs. The PSD Control input pins are labeled as to the MCU function for which they are configured. ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 80C31 Figure 21 shows the bus interface for the 80C31, which has an 8-bit multiplexed address/data bus. The lower address byte is multiplexed with the data bus. The MCU control signals Program Se- lect Enable (PSEN, CNTL2), Read Strobe (RD, Figure 21 ...
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... RD/A16 RESET Note: 1. The A16 and A17 connections are optional non-Page-Mode, AD7-AD0 connects to ADIO7-ADIO0. PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 The 80C251 has two major operating modes: Page mode and Non-page mode. In Non-page 48. mode, the data is multiplexed with the lower ad- dress byte, and Address Strobe (ALE/AS, PD0) is active in every bus cycle ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Figure 23. Interfacing the PSD with the 80C251, with RD and PSEN Inputs 80C251SB 2 P1.0 3 P1.1 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1 P3.0/RXD 13 P3.1/TXD 14 P3.2/INT0 15 P3.3/INT1 16 P3.4/T0 17 P3.5/T1 10 RESET RST PSEN 35 RD/A16 EA RESET Table 18. 80C251 Configurations 80C251 READ/WRITE Configuration Pins ...
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... EA/WAIT 17 BUSW RESET PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 es. In Burst Mode, address A19-A4 are latched internally by the PSD, while the 80C51XA changes the A3-A0 signals to fetch bytes of code. The PSD access time is then measured from ad- dress A3-A0 valid to data in valid. The PSD bus ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 68HC11 Figure 25 shows a bus interface to a 68HC11 where the PSD is configured in 8-bit multiplexed mode with E and R/W settings. The DPLD can be Figure 25. Interfacing the PSD with a 68HC11 68HC11 RESET RESET 19 IRQ 18 XIRQ 2 MODB 34 PA0 33 PA1 ...
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... MCU. The Data Out and macrocell outputs, Direc- tion and Control Registers, and port pin input are all connected to the Port Data Buffer (PDB). PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 The Port pin’s tri-state output driver enable is con- trolled by a two input OR gate whose inputs come from the CPLD AND Array enable product term and the Direction Register ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Figure 26. General I/O Port Architecture DATA OUT REG ADDRESS D Q ALE G MACROCELL OUTPUTS EXT CS READ MUX CONTROL REG DIR REG ENABLE PRODUCT TERM ( .OE ) CPLD- INPUT 52/110 DATA OUT ADDRESS OUTPUT MUX OUTPUT SELECT ...
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... Yes JTAG ISP No Note: 1. Can be multiplexed with other I/O functions. PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 corresponding bit in the Direction Register to ’0.’ The corresponding bit in the Direction Register must not be set to '1' if the pin is defined for a PLD input signal in PSDabel. The PLD I/O mode is 18 ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Table 20. Port Operating Mode Settings Defined in Mode PSDabel MCU I/O Declare pins only PLD I/O Logic equations Data Port (Port A) N/A Address Out Declare pins only (Port A,B) Address In Logic for equation (Port A,B,C,D) Input Macrocells Peripheral I/O Logic equations (Port A) (PSEL0 & 1) ...
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... Figure 27. Peripheral I/O Mode RD PSEL0 PSEL1 VM REGISTER BIT 7 WR PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Peripheral I/O Mode Peripheral I/O mode can be used to interface with external peripherals. In this mode, all of Port A serves as a tri-state, bi-directional data buffer for the MCU. Peripheral I/O Mode is enabled by set- ting Bit 7 of the VM Register to a ’1.’ Figure ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 JTAG In-System Programming (ISP) Port C is JTAG compliant, and can be used for In- System Programming (ISP). You can multiplex JTAG operations with other functions on Port C because In-System Programming (ISP) is not per- formed in normal Operating mode. For more infor- ...
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... MCU. Table 27. Port Data Registers Register Name Data In A,B,C,D Data Out A,B,C,D Output Macrocell A,B,C Mask Macrocell A,B,C Input Macrocell A,B,C Enable Out A,B,C PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Bit 5 Bit 4 Bit 3 Open Open Slew Drain Drain Rate Open Open Slew Drain Drain Rate ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Input Macrocells (IMC) The Input Macrocells (IMC) can be used to latch or store external inputs. The outputs of the Input Macrocells (IMC) are routed to the PLD input bus, and can be read by the MCU. See the section en- titled PLDS, page 33 ...
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... READ MUX DIR REG ENABLE PRODUCT TERM ( .OE ) CPLD - INPUT PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Open Drain – Port C pins can be configured in Open Drain Mode Battery Backup features – PC2 can be configured for a battery input supply, Voltage Stand-by (V PC4 can be configured as a Battery-on Indicator ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Port D – Functionality and Structure Port D has three I/O pins. See Figure ure 31., page 61. This port does not support Ad- dress Out mode, and therefore no Control Register is required. Port D can be configured to perform one or more of the following functions: MCU I/O Mode CPLD Output – ...
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... Chip Select (ECS0-ECS2) consists of one product Figure 31. Port D External Chip Select Signals PT0 PT1 PT2 PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 term that can be configured active High or Low. The output enable of the pin is controlled by either the output enable product term or the Direction Register. (See Figure 31.) ENABLE ( ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 POWER MANAGEMENT All PSD devices offer configurable power saving options. These options may be used individually or in combinations, as follows: All memory blocks in a PSD (primary and secondary Flash memory, and SRAM) are built with power management technology. In ...
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... Note: 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo Bit. 2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo Bit is ’0.’ PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 registers. The blocked signals include MCU control signals and the common CLKIN (PD1) ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 For Users of the HC11 (or compatible) The HC11 turns off its E clock when it sleeps. Therefore, if you are using an HC11 (or compati- ble) in your design, and you wish to use the Pow- er-down mode, you must not connect the E clock to CLKIN (PD1) ...
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... DBE input to PLD AND Array is disconnected, saving power. Bit Not used, and should be set to zero. Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers. PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 65/110 ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 PSD Chip Select Input (CSI, PD2) PD2 of Port D can be configured in PSDsoft Ex- press as PSD Chip Select Input (CSI). When Low, the signal selects and enables the internal Flash memory, EEPROM, SRAM, and I/O blocks for READ or WRITE operations involving the PSD. A ...
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... Figure 34. Reset (RESET) Timing V (min NLNH-PO Power-On Reset RESET PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 The same t OPR after operational after warm reset. Figure CC the timing of the Power-up and warm reset. I/O Pin, Register and PLD Status at Reset Table 33., page 68 PLD status during Power On Reset, warm reset and Power-down mode ...
Page 68
... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Table 33. Status During Power-On Reset, Warm Reset and Power-down Mode Port Configuration Power-On Reset MCU I/O Input mode Valid after internal PSD PLD Output configuration bits are loaded Address Out Tri-stated Data Port Tri-stated Peripheral I/O Tri-stated Register ...
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... PSD I/O. JTAG_ON = PSDsoft_enabled + /* An NVM configuration bit inside the PSD is set by the designer in the PSDsoft Express Configuration utility. PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 This dedicates the pins for JTAG at all 70). All memory times (compliant with IEEE 1149.1 */ Microcontroller_enabled + /* The microcontroller can set a bit at run-time by writing to the PSD register, JTAG Enable ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 JTAG Extensions TSTAT and TERR are two JTAG extension signals enabled by an “ISC_ENABLE” command received over the four standard JTAG signals (TMS, TCK, TDI, and TDO). They are used to speed Program and Erase cycles by indicating status on PSD sig- nals instead of having to scan the status out seri- ally using the standard JTAG channel ...
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... Note: 1. The state of Reset (RESET) does not interrupt (or prevent) JTAG operations if the JTAG signals are dedicated by an NVM Config- uration bit (via PSDsoft Express). However, Reset (RESET) prevents or interrupts JTAG operations if the JTAG enable register is used to enable the JTAG signals. PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 programming procedure. Information for program- ming the device is available directly from ST. ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 AC/DC PARAMETERS These tables describe the AD and DC parameters of the PSD: DC Electrical Specification AC Timing Specification PLD Timing – Combinatorial Timing – Synchronous Clock Mode – Asynchronous Clock Mode – Input Macrocell Timing MCU Timing – READ Timing – ...
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... Turbo Mode I total CC This is the operating power with no EEPROM WRITE or Flash memory Erase cycles in progress. Calculation is based 0mA. OUT PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 = 5.0V (Turbo Mode On) CC Conditions = 8 MHz = 4 MHz = 80 (no additional power above base) ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Table 37. Example of PSD Typical Power Calculation at V Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash memory Access % SRAM access % I/O access Operational Modes % Normal % Power-down Mode Number of product terms used (from fitter report) ...
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... Electrostatic Discharge Voltage (Human Body model) ESD Note: 1. IPC/JEDEC J-STD-020A 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 plied. Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC Characteristic tables that follow are de- rived from tests performed under the Measure- Table 39. Operating Conditions (5V devices) ...
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... Capacitance (for CNTL2/V VPP Note: 1. Sampled only, not 100% tested. 2. Typical values are for T = 25°C and nominal supply voltages. A Figure 37. AC Measurement I/O Waveform 3.0V Test Point 0V Figure 39. Switching Waveforms – Key WAVEFORMS PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Test Condition OUT ) Figure 38 ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Table 45. DC Characteristics (5V devices) Symbol Parameter V Input High Voltage IH V Input Low Voltage IL V Reset High Level Input Voltage IH1 V Reset Low Level Input Voltage IL1 V Reset Pin Hysteresis HYS V (min) for Flash Erase and CC V LKO ...
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... IL1 2. CSI deselected or internal PD is active. 3. PLD is in non-Turbo mode, and none of the inputs are switching. 4. Please see Figure 36., page 72 for the PLD current calculation 0mA OUT PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Conditions 3.0 V < V < 3 3.0 V < V < 3 (Note ...
Page 80
... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Figure 40. Input to Output Disable / Enable INPUT INPUT TO OUTPUT ENABLE/DISABLE Table 47. CPLD Combinatorial Timing (5V devices) Symbol Parameter Conditions CPLD Input Pin/ t Feedback to CPLD PD Combinatorial Output CPLD Input to CPLD t EA Output Enable CPLD Input to CPLD t ER Output Disable ...
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... ARD Delay Minimum Clock MIN CH 2 Period Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount. 2. CLKIN (PD1 CLCL CH CL PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 -70 -90 Min Max Min Max ) 40.0 30.30 CO –10) 66.6 43.48 CO ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Table 50. CPLD Macrocell Synchronous Clock Mode Timing (3V devices) Symbol Parameter Conditions Maximum Frequency 1/(t External Feedback Maximum Frequency f 1/(t MAX Internal Feedback (f ) CNT Maximum 1/(t Frequency Pipelined Data t Input Setup Time S t Input Hold Time H t Clock High Time ...
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... Figure 42. Asynchronous Reset / Preset RESET/PRESET INPUT REGISTER OUTPUT Figure 43. Asynchronous Clock Mode Timing (product term clock) CLOCK INPUT REGISTERED OUTPUT PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 tARPW tARP tCHA tCLA tSA tHA tCOA AI02864 AI02859 83/110 ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Table 51. CPLD Macrocell Asynchronous Clock Mode Timing (5V devices) Symbol Parameter Conditions Maximum Frequency 1/( External Feedback Maximum Frequency f Internal 1/(t +t MAXA SA COA Feedback (f ) CNTA Maximum Frequency 1/(t +t CHA Pipelined Data Input Setup t SA Time Input Hold t HA Time ...
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... Input Hold Time HA t Clock High Time CHA t Clock Low Time CLA Clock to Output t COA Delay CPLD Array t Any macrocell ARD Delay Minimum Clock t 1/f MINA Period PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 -12 -15 Min Max Min Max +t ) 21.7 19.2 COA –10) 27.8 23.8 COA +t ) 33.3 27 CLA 10 ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Figure 44. Input Macrocell Timing (product term clock) PT CLOCK INPUT OUTPUT AI03101 Table 53. Input Macrocell Timing (5V devices) Symbol Parameter t Input Setup Time IS t Input Hold Time IH t NIB Input High Time INH t NIB Input Low Time INL ...
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... NON-MULTIPLEXED BUS CSI RD (PSEN, DS AVPV Note and t are not required for 80C251 in Page Mode or 80C51XA in Burst Mode. AVLX LXAX PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 1 t LXAX ADDRESS VALID t AVQV ADDRESS VALID t SLQV t RLQV t RLRH t EHEL t THEH ADDRESS OUT ...
Page 88
... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Table 55. READ Timing (5V devices) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX t Address Valid to Data Valid AVQV t CS Valid to Data Valid SLQV RD to Data Valid 8-Bit Bus t RLQV RD or PSEN to Data Valid ...
Page 89
... Any input used to select an internal PSD function multiplexed mode latched address generated from ADIO delay to address output on any Port timing has the same timing as DS, LDS, and UDS signals. PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 -12 Conditions Min Max Min Max Min Max ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Figure 46. WRITE Timing ALE/AS A/D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI WR (DS 90/110 t AVLX t LXAX t LVLX ADDRESS VALID t AVWL ADDRESS VALID t SLWL t WLWH t EHEL t THEH t AVPV ADDRESS OUT DATA VALID DATA VALID t DVWH ...
Page 91
... Assuming data is stable before active WRITE signal. 5. Assuming WRITE is active before data becomes valid. 6. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory. PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 -70 Conditions Min Max Min Max Min Max ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Table 58. WRITE Timing (3V devices) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX Address Valid to Leading t AVWL Edge Valid to Leading Edge of WR SLWL t WR Data Setup Time DVWH ...
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... WHWLO t DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling) Q7VQV Note: 1. Programmed to all zero before erase. 2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading. PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Parameter 100,000 2 Min. Typ. Max. ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Figure 47. Peripheral I/O READ Timing ALE/AS A/D BUS CSI RD Table 61. Port A Peripheral Data Mode READ Timing (5V devices) Symbol Parameter Address Valid to Data t AVQV–PA Valid t CSI Valid to Data Valid SLQV– Data Valid t RLQV– Data Valid 8031 Mode ...
Page 95
... WR has the same timing as the E, LDS, UDS, WRL, and WRH signals. 3. Any input used to select Port A Data Peripheral mode. 4. Data is already stable on Port A. 5. Data stable on ADIO pins to data on Port A. PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 -12 Conditions Min Max Min Max Min Max ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Table 64. Port A Peripheral Data Mode WRITE Timing (3V devices) Symbol Parameter Data Propagation Delay WLQV–PA t Data to Port A Data Propagation Delay DVQV– Invalid to Port A Tri-state WHQZ–PA Note has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode). ...
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... Symbol Parameter t V Detection to V BVBH STBY STBYON V Off Detection to V STBY t BXBL Low Note timing is measured at V STBYON CC PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Conditions 1 Output High (Note ) Output STBYON 1 (Note ) ramp rate of 2 ms. Conditions 1 Output High (Note ) Output STBYON ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Figure 50. ISC Timing t ISCCH TCK TDI/TMS ISC OUTPUTS/TDO ISC OUTPUTS/TDO Table 69. ISC Timing (5V devices) Symbol Parameter Clock (TCK, PC1) Frequency (except for t ISCCF PLD) Clock (TCK, PC1) High Time (except for t ISCCH PLD) Clock (TCK, PC1) Low Time (except for ...
Page 99
... Symbol Parameter t ALE Access Time from Power-down LVDV Maximum Delay from APD Enable to t CLWH Internal PDN Valid Signal Note the period of CLKIN (PD1). CLCL PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 -12 Conditions Min Max Min Max Min Max 1 (Note ) 1 40 (Note ) 1 ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 PACKAGE MECHANICAL Figure 51. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Drawing QFP-A Note: Drawing is not to scale. 100/110 ...
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... Table 73. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Dimensions Symb. Typ 2. 13.20 D1 10.00 D2 7.80 E 13.20 E1 10.00 E2 7.80 e 0.65 L 0. PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 mm Min. Max. Typ. 2.35 0.25 1.80 2.10 0.079 0.22 0.38 0.11 0.23 13.15 13.25 0.520 9.95 10.05 0.394 – – 0.307 13.15 13.25 0.520 9.95 10.05 0.394 – – 0.307 – – ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Figure 52. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Drawing PLCC-B Note: Drawing is not to scale. Table 74. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Dimensions Symbol Typ 1.27 R 0.89 N ...
Page 103
... Figure 53. TQFP64 - 64-lead Thin Quad Flatpack, Package Outline QFP-A Note: Drawing is not to scale. PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 103/110 ...
Page 104
... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Table 75. TQFP64 - 64-lead Thin Quad Flatpack, Package Mechanical Data Symb. Typ 0.10 A2 1.40 3.5° 16.00 D1 14.00 D2 12.00 E 16.00 E1 14.00 E2 12.00 e 0.80 L 0.60 L1 1. 104/110 mm Min. Max. Typ. 1.42 1.54 0.07 0.14 0.004 1.36 1.44 0.055 0.0° 7.0° 3.5° 0.33 0.38 0.014 0.17 15.90 16.10 0.630 13.98 14.03 0.551 11.95 12.05 0.472 15.90 16.10 0.630 13.98 14.03 0.551 11.95 12.05 0.472 ...
Page 105
... Temperature Range blank = 0 to 70° C (commercial –40 to 85° C (industrial) Option T = Tape & Reel Packing For a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact your nearest ST Sales Office. PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 PSD8 – ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 APPENDIX A. PQFP52 PIN ASSIGNMENTS Table 77. PQFP52 Connections (Figure 2) Pin Number Pin Assignments 106/110 Pin Number PD2 27 PD1 28 PD0 29 PC7 30 PC6 31 PC5 32 PC4 ...
Page 107
... Table 78. PLCC52 Connections (Figure 3) Pin Number Pin Assignments PC2 ( PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Pin Number GND 27 PB5 28 PB4 29 PB3 30 PB2 31 PB1 32 PB0 33 PD2 34 PD1 35 PD0 36 PC7 37 PC6 38 PC5 39 PC4 40 ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 APPENDIX C. TQFP64 PIN ASSIGNMENTS Table 79. TQFP64 Connections (Figure 4) Pin Number Pin Assignments 108/110 Pin Number PD2 33 PD1 34 PD0 35 PC7 36 PC6 ...
Page 109
... Correct Instructions (Table 9); update disclaimer, Title for EDOCS application 17-Nov-03 3.3 Correct package references (Figure 1) Reformatted (adjust RPN list); added Table 8; added ‘U’ package (64-pin) (Figure 1, 4, 53; 04-Jun-04 4.0 Table 75, 76, 79); 5V split from original PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Description of Revision 109/110 ...
Page 110
... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequ of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are s to change without notice ...