M48Z18-100PC1 STMicroelectronics, M48Z18-100PC1 Datasheet - Page 10

• Manufacturer Part Number: M48Z18-100PC1
• Description: IC NVSRAM 64KBIT 100NS 28DIP
• Manufacturer: STMicroelectronics

Specifications of M48Z18-100PC1

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 64K (8K x 8)
• Speed: 100ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP Module (600 mil), 28-EDIP
• Data Bus Width: 8 bit
• Organization: 8 Kb x 8
• Interface Type: Parallel
• Access Time: 100 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Operating Current: 80 mA
• Maximum Operating Temperature: 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Capacitance, Input: 10 pF
• Capacitance, Output: 10 pF
• Current, Input, Leakage: ±1 μA
• Current, Operating: 80 mA
• Current, Output, Leakage: ±1
• Data Retention: 11 yrs.
• Density: 64K
• Package Type: PCDIP28
• Power Dissipation: 1 W
• Temperature, Operating: 0 to +70 °C
• Time, Access: 100 ns
• Time, Fall: ≤5 ns
• Time, Rise: ≤5 ns
• Voltage, Input, High: 4.8 to 5.8 V
• Voltage, Input, Low: 0.8 V
• Voltage, Output, High: 2.4 V
• Voltage, Output, Low: 0.4 V
• Voltage, Supply: 4.5 to 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2877-5

Operation modes
2.3
Note:
10/20
Table 4.
1. Valid for ambient operating temperature: T
2. C
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Data retention mode
With valid V
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when V
become high impedance, and all inputs are treated as “Don't care.”
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
user can be assured the memory will be in a write protected state, provided the V
is not less than t
into the deselect window during the time the device is sampling V
of the power supply lines is recommended.
When V
preserves data. The internal button cell will maintain data in the M48Z08/18 for an
accumulated period of at least 11 years when V
As system power returns and V
power supply is switched to external V
(min) plus t
inadvertent write cycles prior to system stabilization. Normal RAM operation can resume t
after V
application note AN1012.
t
t
WHQX
WLQZ
Symbol
t
noted).
t
t
t
t
t
t
t
t
t
t
t
t
WLWH
WHAX
DVWH
WHDX
AVWH
EHDX
AVWL
EHAX
DVEH
AVEH
AVEL
ELEH
AVAV
L
= 30 pF.
(2)(3)
CC
(2)(3)
CC
exceeds V
drops below V
rec
CC
WRITE mode AC characteristics
WRITE cycle time
Address valid to WRITE enable low
Address valid to chip enable 1 low
WRITE enable pulse width
Chip enable low to chip enable 1 high
WRITE enable high to address transition
Chip enable high to address transition
Input valid to WRITE enable high
Input valid to chip enable 1 high
WRITE enable high to input transition
Chip enable high to input transition
WRITE enable low to output Hi-Z
Address valid to WRITE enable high
Address valid to chip enable high
WRITE enable high to output transition
(min). E should be kept high as V
applied, the M48Z08/18 operates as a conventional BYTEWIDE™ static
F
. The M48Z08/18 may respond to transient noise spikes on V
PFD
CC
(max). For more information on battery storage life refer to the
Parameter
SO
falls within the V
, the control circuit switches power to the internal battery which
Doc ID 2424 Rev 7
CC
rises above V
(1)
A
CC
= 0 to 70 °C; V
. Write protection continues until V
PFD
(max), V
CC
CC
SO
CC
rises past V
is less than V
, the battery is disconnected, and the
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where
Min
100
PFD
80
80
10
10
50
30
80
80
10
M48Z08/M48Z18
0
0
5
5
(min) window. All outputs
PFD
SO
CC
(min) to prevent
.
. Therefore, decoupling
Max
50
M48Z08, M48Z18
CC
PFD
reaches V
CC
(min), the
CC
that reach
Unit
fall time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PFD
rec