DS28EC20+ Maxim Integrated Products, DS28EC20+ Datasheet - Page 23

• Manufacturer Part Number: DS28EC20+
• Description: IC EEPROM 20KBIT TO92-3
• Manufacturer: Maxim Integrated Products

Specifications of DS28EC20+

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 20K (256 x 80)
• Interface: 1-Wire Serial
• Operating Temperature: -40°C ~ 85°C
• Package / Case: TO-92-3 (Standard Body), TO-226
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Speed: -

Slave-to-Master
A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below V
read low time t
line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When
responding with a 1, the DS28EC20 does not hold the data line low at all, and the voltage starts rising as soon as
t
The sum of t
define the master sampling window (t
For the most reliable communication, t
but no later than t
guarantees sufficient recovery time t
specified herein applies only to a single DS28EC20 attached to a 1-Wire line. For multidevice configurations, t
needs to be extended to accommodate the additional 1-Wire device input capacitance. Alternatively, an interface
that performs active pullup during the 1-Wire recovery time such as the DS2482-x00 or DS2480B 1-Wire line
drivers can be used.
IMPROVED NETWORK BEHAVIOR (SWITCHPOINT HYSTERESIS)
In a 1-Wire environment, line termination is possible only during transients controlled by the bus master (1-Wire
driver). 1-Wire networks, therefore, are susceptible to noise of various origins. Depending on the physical size and
topology of the network, reflections from end points and branch points can add up or cancel each other to some
extent. Such reflections are visible as glitches or ringing on the 1-Wire communication line. Noise coupled onto the
1-Wire line from external sources can also result in signal glitching. A glitch during the rising edge of a time slot can
cause a slave device to lose synchronization with the master and, consequently, result in a Search ROM command
coming to a dead end or cause a device-specific function command to abort. For better performance in network
applications, the DS28EC20 uses a new 1-Wire front-end, which makes it less sensitive to noise.
The 1-Wire front-end of the DS28EC20 differs from traditional slave devices in three characteristics:
1) There is additional low-pass filtering in the circuit that detects the falling edge at the beginning of a time slot.
2) There is a hysteresis at the low-to-high switching threshold V
3) There is a time window specified by the rising edge hold-off time t
Devices that have the parameters V
front-end.
Figure 12. Noise Suppression Scheme
RL
is over.
This reduces the sensitivity to high-frequency noise. This additional filtering does not apply at overdrive speed.
below V
they extend below V
appear late after crossing the V
taken as the beginning of a new time slot (Figure 12, Case C, t
TH
V
RL
HY
RL
- V
V
+ δ (rise time) on one side and the internal timing generator of the DS28EC20 on the other side
V
PUP
0V
is expired. During the t
HY
TH
, it is not recognized (Figure 12, Case A). The hysteresis is effective at any 1-Wire speed.
MSRMAX
TH
. After reading from the data line, the master must wait until t
- V
HY
Case A
threshold (Figure 12, Case B, t
TH
HY
MSRMIN
REC
threshold and extend beyond the t
and t
RL
RL
should be as short as permissible, and the master should read close to
window, when responding with a 0, the DS28EC20 starts pulling the data
for the DS28EC20 to get ready for the next time slot. Note that t
to t
REH
MSRMAX
specified in their electrical characteristics use the improved 1-Wire
23 of 27
) in which the master must perform a read from the data line.
t
GL
Case B
t
REH
TH
GL
GL
. If a negative glitch crosses V
≥ t
< t
REH
REH
REH
REH
during which glitches are ignored, even if
).
). Deep voltage droops or glitches that
window cannot be filtered out and are
t
REH
t
Case C
GL
SLOT
TH
is expired. This
but does not go
TL
until the
REC
REC