HT6256 Honeywell Microelectronics & Precision Sensors, HT6256 Datasheet - Page 2

• Manufacturer Part Number: HT6256
• Description: IC SRAM 256KBIT 20MHZ 28DIP
• Manufacturer: Honeywell Microelectronics & Precision Sensors
• Series: HTMOS™r

Specifications of HT6256

• Format - Memory: RAM
• Memory Type: SRAM
• Memory Size: 256K (32K x 8)
• Speed: 20MHz
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -55°C ~ 225°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

HT6256
TRUTH TABLE
FUNCTIONAL DIAGRAM
SIGNAL DEFINITIONS
A: 0-14
DQ: 0-7
NCS
NWE
NOE
CE*
NCS
H
X
L
L
NCS
NWE
NOE
CE*
A:9-11, 14
A:0-8,12-13
Address input pins which select a particular eight-bit word within the memory array.
Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS
forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and
disables all input buffers. If this signal is not used it must be connected to VSS.
Negative write enable, when at a low level activates a write operation and holds the data output drivers in
a high impedance state. When at a high level NWE allows normal read operation.
Negative output enable, when at a high level holds the data output drivers in a high impedance state. When
at a low level, the data output driver state is defined by NCS and NWE. If this signal is not used it must be
connected to VSS.
External control of Chip Enable is an extra feature available only in other package options. Chip enable, when
at a high level allows normal operation. When at a low level CE forces the SRAM to a precharge condition,
holds the data output drivers in a high impedance state and disables all the input buffers except the NCS input
buffer. If this signal is not used it must be connected to VDD.
CE*
H
H
X
L
NWE
XX
XX
H
L
4
11
NOE
XX
XX
X
L
Decoder
Deselected
Disabled
Row
MODE
Read
Write
WE • CS • CE
NWE • CS • CE • OE
(0 = high Z)
Data Out
2
•
•
•
Data In
High Z
High Z
DQ
Column Decoder
Data Input/Output
32,768 x 8
Memory
•
Array
•
•
NOE=H: High Z output state maintained for
Notes:
XX: VSS VI VDD
Signal
All controls must be
enabled for a signal to
pass. (#: number of
buffers, default = 1)
X: VI=VIH or VIL
NCS=X, CE=X, NWE=X
8
#
1 = enabled
8
Signal
DQ:0-7