AT49LH004-33JX Atmel, AT49LH004-33JX Datasheet - Page 11

• Manufacturer Part Number: AT49LH004-33JX
• Description: IC FLASH 4MBIT 33MHZ 32PLCC
• Manufacturer: Atmel

Specifications of AT49LH004-33JX

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 33MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 32-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5
Figure 7-3.
Table 7-4.
Note:
3383D–FLASH–6/05
FWH4/LFRAME
FWH/LAD[3:0]
Clock
Cycle
3 - 9
10
11
12
13
14
15
16
17
1
2
FWH Write Cycle
1. Field contents are valid on the rising edge of the present clock cycle.
CLK
Field Name
MADDR
RSYNC
START
MSIZE
IDSEL
DATA
DATA
TAR0
TAR1
TAR0
TAR1
FWH Write Cycle
FWH Write Cycle
1110b
START
1
0000b to 1111b
FWH/LAD[3:0]
0000b (ready)
Field Value
1111b (float)
1111b (float)
IDSEL
IDSEL
(indicates
1 byte)
1110b
YYYY
0000b
1111b
1111b
YYYY
YYYY
FWH write cycles are used to send commands to the device and to program data into the
memory array.
Valid FWH write cycles begin with a START field of 1110b being sent to the device. Following
the IDSEL, MADDR, and MSIZE fields, the master sends one byte of data to the FWH device
during the next two clock cycles. The data is sent one nibble at a time with the low nibble being
output first followed by the high nibble. After the data has been sent, the master will send a
2-clock TAR field to the FWH device to indicate that it is turning control of the LPC bus back
over to the FWH. After the second clock of the TAR phase, the FWH device assumes control
of the bus and drives a “ready” SYNC field to verify that it has received the data. The FWH
device will then send a 2-clock TAR field to the master to indicate that it is turning control of
the bus back over to the master.
2
A27-A24 A23-A20 A19-A16
(1)
3
Float then OUT
FWH/LAD[3:0]
OUT then float
4
Float then IN
IN then float
Direction
OUT
IN
IN
IN
IN
IN
IN
5
A15-A12
MADDR
6
A11-A8
Comments
FWH4/LFRAME must be active (low) for the device to respond. Only the last
START field (before FWH4/LFRAME transitioning high) should be recognized. The
START field contents indicate a FWH memory write cycle.
Indicates which FWH memory device should respond. If the IDSEL field matches
the strapping values on ID[3:0], then that particular device will respond to
subsequent commands.
These seven clock cycles make up the 28-bit memory address. YYYY is one
nibble of the entire address. Addresses are transferred with the most significant
nibble first.
The MSIZE field indicates how many bytes will be transferred. The device only
supports single-byte operations, so MSIZE must be 0000b.
YYYY is the least significant nibble of the data byte. The data byte is either any
valid Flash command or the data to be programmed into the memory array.
YYYY is the most significant nibble of the data byte.
In this clock cycle, the master has driven the bus to all 1s and then floats the bus
prior to the next clock cycle. This is the first part of the bus “turn-around cycle”.
The device takes control of the bus during this clock cycle.
During this clock cycle, the device will generate a “ready” SYNC indicating that the
data byte has been received.
The FWH memory device drives the bus to 1111b to indicate a turn-around cycle.
The FWH memory device floats its outputs, and the master regains control of the
bus during this clock cycle.
7
A7-A4
8
A3-A0
9
0000b
MSIZE
10
D3-D0
DATA
11
D7-D4
DATA
12
1111b
TAR0
13
High-Z
TAR1
14
AT49LH004
RSYNC
0000b
15
1111b
TAR0
16
High-Z
TAR1
17
11