AT49LH00B4-33JC SL383 Atmel, AT49LH00B4-33JC SL383 Datasheet - Page 17

• Manufacturer Part Number: AT49LH00B4-33JC SL383
• Description: IC FLASH 4MBIT 33MHZ 32PLCC
• Manufacturer: Atmel

Specifications of AT49LH00B4-33JC SL383

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 33MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 32-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 7-6.
Table 7-8.
Note:
3379C–FLASH–3/05
FWH4/LFRAME
FWH/LAD[3:0]
Clock Cycle
3 - 10
11
12
13
14
15
16
17
1
2
1. Field contents are valid on the rising edge of the present clock cycle.
CLK
LPC Write Cycle
LPC Write Cycle
CYCTYPE +
Field Name
MADDR
RSYNC
0000b
START
START
DATA
DATA
TAR0
TAR1
TAR0
TAR1
DIR
1
CYCTYPE
011xb
+ DIR
2
A31-A28
FWH/LAD[3:0]
0000b (ready)
Field Value
1111b (float)
1111b (float)
3
0000b
011xb
1111b
1111b
YYYY
YYYY
YYYY
A27-A24
4
A23-A20 A19-A16
(1)
5
Float then OUT
FWH/LAD[3:0]
OUT then float
Float then IN
IN then float
Direction
MADDR
6
OUT
A15-A12
IN
IN
IN
IN
IN
7
A11-A8
8
Comments
FWH4/LFRAME must be active (low) for the device to
respond. Only the last START field (before FWH4/LFRAME
transitioning high) should be recognized. The START field
contents indicate an LPC cycle.
Indicates that the cycle type is an LPC memory cycle and the
direction of the transfer is a write.
These eight clock cycles make up the 32-bit memory address.
YYYY is one nibble of the entire address. Addresses are
transferred with the most significant nibble first.
YYYY is the least significant nibble of the data byte. The data
byte is either any valid Flash command or the data to be
programmed into the memory array.
YYYY is the most significant nibble of the data byte.
In this clock cycle, the master has driven the bus to all 1s and
then floats the bus prior to the next clock cycle. This is the first
part of the bus “turn-around cycle”.
The device takes control of the bus during this clock cycle.
During this clock cycle, the device will generate a “ready”
SYNC indicating that the data byte has been received.
The LPC memory device drives the bus to 1111b to indicate a
turn-around cycle.
The LPC memory device floats its outputs, and the master
regains control of the bus during this clock cycle.
A7-A4
9
A3-A0
10
D3-D0
DATA
11
D7-D4
DATA
12
1111b
TAR0
13
High-Z
AT49LH00B4
TAR1
14
RSYNC
0000b
15
1111b
TAR0
16
High-Z
TAR1
17
17