AT49LH00B4-33TC ATMEL [ATMEL Corporation], AT49LH00B4-33TC Datasheet
AT49LH00B4-33TC
Related parts for AT49LH00B4-33TC
AT49LH00B4-33TC Summary of contents
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... TSOP Description The AT49LH00B4 is a Flash memory device designed for use in PC and notebook BIOS applications. The device complies with version 1.1 of Intel’s LPC Interface Spec- ification, providing support for both FWH and LPC memory read and write cycles. The device can also automatically detect the memory cycle type to allow the AT49LH00B4 to be used as a FWH with Intel chipsets LPC Flash with non-Intel chipsets ...
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... BIOS routines to be developed and added while still main- taining the same overall device density. The memory array of the AT49LH00B4 can be sectored in two ways simply by using two differ- ent erase commands. Using one erase command allows the device to contain a total of eleven sectors comprised of a 64-Kbyte boot sector, six 64-Kbyte sectors, a 32-Kbyte sector, a 16- Kbyte sector, and two 8-Kbyte sectors ...
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... Type Size (Bytes) 64K 64K 64K 64K 64K 64K 64K 32K 16K 8K 8K AT49LH00B4 Address Range 070000H - 07FFFFH 060000H - 06FFFFH 050000H - 05FFFFH 040000H - 04FFFFH 030000H - 03FFFFH 020000H - 02FFFFH 010000H - 01FFFFH 008000H - 00FFFFH 004000H - 007FFFH 002000H - 003FFFH 000000H - 001FFFH Interface ...
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... Any unused GPI pins must not be left floating. These pins are used as the A[10:6] pins in the A/A Mux interface. A[10:0] ADDRESS INPUTS: These pins are used for inputting the multiplexed address values when using the A/A Mux interface. The addresses are latched by the rising and falling edge of R/C pin. AT49LH00B4 4 Interface FWH/LPC A/A Mux X ...
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... V These pins are used as the RDY/BSY and I/O[7:4] pins in the A/A Mux interface. 3379B–FLASH–9/03 voltages may produce spurious results and should not be CC and V requirements AT49LH00B4 Interface FWH/LPC A/A Mux X is less than and V ...
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... These field sequences are detailed in the FWH Interface Operation and LPC Interface Opera- tion sections. Since the AT49LH00B4 can be used as either a FWH Flash or an LPC Flash, the device is capable of automatically detecting which type of memory cycle is being performed. For a FWH/LPC cycle, the host will drive the FWH4/LFRAME pin low for one or more clock cycles to initiate the operation ...
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... GB addressable space if 16 FWH memory devices (256 MB each) were used in a system. The AT49LH00B4 only decodes the last six MADDR nibbles (A23 - A0) and ignores address bits A27 - A23 and A21 - A19. Address bit A22 is used to determine whether reads or writes to the device will be directed to the memory array (A22 = the register space (A22 = 0) ...
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... LPC bus back over to the master. Figure 2 shows a FWH read cycle that requires three SYNC clocks to access data from the memory array. AT49LH00B4 8 SYNC Type RSYNC (Ready SYNC) – Synchronization has been achieved with no error. ...
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... YYYY is the most significant nibble of the data byte. 1111b OUT then float The FWH memory device drives the bus to 1111b to indicate a turn-around cycle. Float then IN The FWH memory device floats its outputs, and the master regains control of the bus during this clock cycle. AT49LH00B4 ...
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... DATA 12 DATA 13 TAR0 14 TAR1 1111b (float) 15 RSYNC 0000b (ready) 16 TAR0 17 TAR1 1111b (float) Note: 1. Field contents are valid on the rising edge of the present clock cycle. AT49LH00B4 A15-A12 A11-A8 A7-A4 A3-A0 MADDR (1) FWH/LAD[3:0] Direction Comments 1110b IN FWH4/LFRAME must be active (low) for the device to respond. Only the last START field (before FWH4/LFRAME transitioning high) should be recognized ...
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... A0) memory address. The 32 address bits allow for the provisioning to access memory space. The AT49LH00B4 only decodes the last six MADDR nibbles (A23 - A0) and ignores address bits A31 - A24. Address bit A23 is used to determine whether reads or writes to the device will be directed to the memory array (A23 = the register space (A23 = 0) ...
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... TAR field to the master to indicate that it is turning control of the LPC bus back over to the master. Figure 5 shows a LPC read cycle that requires three SYNC clocks to access data from the memory array. AT49LH00B4 12 SYNC Type RSYNC (Ready SYNC) – Synchronization has been achieved with no error. ...
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... YYYY is the most significant nibble of the data byte. 1111b OUT then float The LPC memory device drives the bus to 1111b to indicate a turn-around cycle. Float then IN The LPC memory device floats its outputs, and the master regains control of the bus during this clock cycle. AT49LH00B4 ...
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... MADDR 11 DATA 12 DATA 13 TAR0 14 TAR1 1111b (float) 15 RSYNC 0000b (ready) 16 TAR0 17 TAR1 1111b (float) Note: 1. Field contents are valid on the rising edge of the present clock cycle. AT49LH00B4 A27-A24 A23-A20 A19-A16 A15-A12 A11-A8 A7-A4 MADDR (1) FWH/LAD[3:0] Direction Comments 0000b IN FWH4/LFRAME must be active (low) for the device to respond ...
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... Table 5 and Table 9) and no internal Flash operation will be attempted. When the FWH4/LFRAME pin has been driven low to abort a cycle, the host may issue a START field of 1111b (stop/abort) to return the interface to the ready mode. 3379B–FLASH–9/03 AT49LH00B4 15 ...
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... The Write Protect (WP) pin, which operates independently from the TBL pin, serves the same basic function as the TBL pin for the remaining sectors except the top boot sector. When the WP pin is held low, program and sector erase operations to sectors 9 through 0 will not be allowed. AT49LH00B4 16 using the FWH/LPC interface and t PHFV ...
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... Address Range 070000H - 07FFFFH 060000H - 06FFFFH 050000H - 05FFFFH 040000H - 04FFFFH 030000H - 03FFFFH 020000H - 02FFFFH 010000H - 01FFFFH 008000H - 00FFFFH 004000H - 007FFFH 002000H - 003FFFH 000000H - 001FFFH AT49LH00B4 Hardware Write Protection TBL ...
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... The Lock-Down bit is only cleared upon a device reset with RST or INIT or after a power-up. The current lock down status of a particular sector can be determined by reading the corresponding Lock-Down bit. AT49LH00B4 18 Register Memory Address Associated ...
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... RST or INIT signals) or power-cycled. Sector is not write-locked. Normal program and erase operations to the sector can occur. Sector is write-locked. Program and erase operations to the sector are prevented. This is the default state. Register Memory Address FWH Mode FFBC0100H AT49LH00B4 LPC Mode Register Type FF7C0100H Read Only 19 ...
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... If there is a mismatch, the device will ignore the remainder of the cycle. The device will then enter standby mode when the FWH4/LFRAME pin is high and no internal operation is in progress. The FWH/LAD[3:0] pins will also be placed in a high-impedance state. Table 16. FWH Multiple Device Selection 0 (Boot Device) AT49LH00B4 20 Name Description Reserved Reserved for future use ...
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... Device ID3 ID2 AT49LH00B4 ID Strapping Pins ID1 ID0 ...
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... RDY/BSY: The open-drain Ready/Busy output pin provides a hardware method of detecting the end of a program or erase operation. RDY/BSY is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. AT49LH00B4 22 RST (1)(2) ...
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... Sector The Address to Write 40H or 10H be Programmed Any Address Write 70H Any Address Write 50H Any Address Write 90H AT49LH00B4 2nd Command Cycle Type Address Data Read Any Address Data OUT Write Any Address in D0H the Sector Write Any Address in ...
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... CLEAR STATUS REGISTER: Error flags (SR[5,4,1]) in the Status Register can only be set to “1”s by the WSM and can only be reset by the Clear Status Register command. Therefore error is detected, the Status Register must be cleared before beginning another operation to avoid ambiguity. AT49LH00B4 24 3379B–FLASH–9/03 ...
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... The program operation failed. If SR[5,4] are 1, then there was a command sequence error. 0 Sector is unlocked. The sector being erased or programmed is unlocked (not protected). 1 Sector is hardware write protected or write-locked. The sector being erased or programmed is either hardware write protected by the TBL or WP pin write-locked. Address 000000H 000001H AT49LH00B4 Data 1FH EDH 25 ...
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... Interface) I Program or Erase Current PP Notes: 1. All currents are in RMS unless otherwise noted. These currents are valid for all packages 0 0 AT49LH00B4 26 *NOTICE: (1)(2) + 2.0V for periods <20 ns. CC Test Condition (1) Case Temperature Conditions Voltage range of all inputs FWH4/ LFRAME = ...
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... V OUT CC ≤ < ≥ > (1) 0 0.6 V load CC CC (1) 0 0.2 V load 0 OUT OUT AT49LH00B4 Min Max 0 1. -0.5 0.3 V 0. Min Max - -17 OUT Note 2 - -17 OUT ...
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... Notes: 1. PCI components must work with any clock frequency between nominal DC and 33 MHz. Frequencies less than16 MHz may be guaranteed by design rather than testing. 2. Applies only to rising edge of signal. Clock Waveform AT49LH00B4 28 Condition peak-to-peak t CYC t HIGH 0 LOW ...
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... Reset Active Time after Power Stable Reset Active Time after CLK Stable (2) Reset Active to Output Float Delay CLK V TEST t VAL FWH/LAD[3:0] (Valid Output Data) FWH/LDA[3:0] (Float Output Data) t OFF CLK t SU Inputs Valid AT49LH00B4 Min 100 ...
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... A reset latency of 20 µs will occur if a reset procedure is performed during a programming or erase operation. AC Waveform for Reset Operation RST FWH4/LFRAME Programming and Erase Times Parameter (2) Byte Program Time (2) Sector Erase Time Notes: 1. Typical values measured Excludes system-level overhead. AT49LH00B4 30 of overdrive over PLPH PHFV ...
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... V min -100 µ min this specification is not CC (1)(2) ( required from the latter of RDY/BSY or RST going high until addresses are valid. t PLRH t t PLPH PHAV AT49LH00B4 Min Max 0 0 -0.5 0.8 +10 0.85 V min 0 0 Min ...
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... PHAV RST V IL AT49LH00B4 32 (1)( after the rising edge of R/C without impact on t GLQV t AVAV Row Address Column Address Stable Stable t t CLAX AVCH t CHAX t CHQV High-Z t GLQX Min Max 250 50 50 ...
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... E = Read status register data F = Ready to write another command 3379B–FLASH–9/03 (1) = 3.0V to 3.6V AVCH t CLAX t t PHWL WHWL t WLWH t WHDX t DVWH D IN AT49LH00B4 Min Max 1 100 100 50 150 150 CHAX t CHWH t WHGL t WHSV Valid ...
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... Ordering Information I (mA) CC Active Standby 20 0.03 32J 32-lead, Plastic J-leaded Chip Carrier Package (PLCC) 40T 40-lead, Thin Small Outline Package (TSOP) AT49LH00B4 34 Ordering Code AT49LH00B4-33JC AT49LH00B4-33TC Package Type Package Operation Range 32J Extended Commercial 40T (0° to 85° C) 3379B–FLASH–9/03 ...
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... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 3379B–FLASH–9/03 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) AT49LH00B4 0.318(0.0125) 0.191(0.0075 COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM A 3.175 – ...
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... Atmel Corporation 2003. All rights reserved. Atmel ® subsidiaries. Intel is a registered trademark of Intel Corporation. Other terms and product names may be the trademarks of others. Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 ...