AT49LH00B4-33TC ATMEL [ATMEL Corporation], AT49LH00B4-33TC Datasheet - Page 32
AT49LH00B4-33TC
Manufacturer Part Number
AT49LH00B4-33TC
Description
4-megabit Top Boot, Bottom Partitioned Firmware Hub and Low-Pin Count Flash Memory
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT49LH00B4-33TC.pdf
(36 pages)
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A/A Mux Interface Read-only Operations
Note:
A/A Mux Read Timing Diagram
32
Symbol
t
t
t
t
t
t
t
t
t
t
t
AVAV
AVCL
CLAX
AVCH
CHAX
CHQV
GLQV
PHAV
GLQX
GHQZ
QXGH
ADDRESSES
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE may be delayed up to t
3. T
AT49LH00B4
C
RST
Parameter
Read Cycle Time
Row Address Setup to R/C Low
Row Address Hold from R/C Low
Column Address Setup to R/C High
Column Address Hold from R/C High
R/C High to Output Delay
OE Low to Output Delay
RST High to Row Address Setup
OE Low to Output in Low-Z
OE High to Output in High-Z
Output Hold from OE High
R/C
I/O
WE
OE
= 0° C to +85° C
V
V
V
V
V
V
V
V
V
V
V
V
OH
OL
IH
IH
IH
IH
IH
IL
IL
IL
IL
IL
,
V
CC
t
PHAV
= 3.0V to 3.6V.
(2)
CHQV
t
(2)
AVCL
- t
GLQV
Row Address
Stable
after the rising edge of R/C without impact on t
t
CLAX
High-Z
Column Address
t
(1)(3)
AVCH
Stable
t
AVAV
t
GLQX
t
CHAX
t
CHQV
Data Valid
t
CHQV
GLQV
.
Min
250
Next Address
50
50
50
50
1
0
0
Stable
t
t
QXGH
GHQZ
Max
150
50
50
3379B–FLASH–9/03
High-Z
Units
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
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