AT49LH00B4-33TC ATMEL [ATMEL Corporation], AT49LH00B4-33TC Datasheet - Page 23

• Manufacturer Part Number: AT49LH00B4-33TC
• Description: 4-megabit Top Boot, Bottom Partitioned Firmware Hub and Low-Pin Count Flash Memory
• Manufacturer: ATMEL [ATMEL Corporation]

Device
Operation
Table 19. Command Definitions
Notes:
3379B–FLASH–9/03
Command
Read Array
Sector Erase
Uniform Sector
Erase
Byte Program
Read Status Register
Clear Status Register
Product ID Read
(1)(2)
1. The sector must not be hardware write protected or write-locked when attempting sector erase or program operations.
2. Sub-sectors are sectors 3, 2, 1, and 0; the main sectors are sectors 10 through 4. Refer to the Device Memory Map and
3. Either 40H or 10H is recognized by the device as the byte program command.
4. Following the Product ID Read command, read operations will access manufacturer and device ID information. Refer to
Attempts to issue a sector erase or byte program command to a hardware write protected or write-locked sector will fail.
Table 10 for sector sizes and address ranges. The Uniform Sector Erase command can be used to erase all sub-sectors at
one time to allow uniform 64-Kbyte sectors to be erased. A Uniform Sector Erase command issued to any address in any
one of the sub-sectors will cause all the sub-sectors to be erased provided that all of the sub-sectors are not protected or
write-locked. The standard Sector Erase command can be used to erase both the sub-sectors and the main sectors, allow-
ing a single erase command to be used to erase any sector in the memory array.
Table 21 for Product ID addresses and data.
(1)(2)
(1)(3)
(4)
Command
Cycles
1+
2
2
2
2
1
2
The FWH/LPC and A/A Mux interfaces should be considered hardware interfaces that can be
used to transfer commands and data to and from the device. The device commands detailed
in Table 19 can be issued using either interface.
Since the FWH/LPC interface communicates using a 4-bit data bus and the A/A Mux interface
utilizes an 8-bit data bus, the number of interface bus cycles needed to perform an operation
will vary. For example, when using the FWH/LPC interface, 17 PCI clock cycles are required
for a FWH or LPC memory write cycle. Therefore, for one “write” device command cycle,
17 FWH/LPC bus cycles are needed. Likewise, for one “read” device command cycle using
the FWH/LPC interface, 19 FWH/LPC bus cycles are required.
Type
Write
Write
Write
Write
Write
Write
Write
1st Command Cycle
be Programmed
The Address to
Any Address in
Any Address in
Any Address
Any Address
Any Address
Any Address
the Sector
the Sector
Address
40H or 10H
Data
FFH
21H
20H
70H
50H
90H
Type
Read
Write
Write
Write
Read
Read
2nd Command Cycle
be Programmed
Any Address in
Any Address in
The Address to
Any Address
Any Address
AT49LH00B4
ID Address
the Sector
the Sector
Address
Data OUT
Register
Data IN
ID Data
Status
Data
D0H
D0H
Data
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