AT28HC64BF-12PU Atmel, AT28HC64BF-12PU Datasheet

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AT28HC64BF-12PU

Manufacturer Part Number
AT28HC64BF-12PU
Description
IC EEPROM 64KBIT 120NS 28DIP
Manufacturer
Atmel
Datasheets

Specifications of AT28HC64BF-12PU

Format - Memory
EEPROMs - Parallel
Memory Type
EEPROM
Memory Size
64K (8K x 8)
Speed
120ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
1. Description
The AT28HC64BF is a high-performance electrically-erasable and programmable
read-only memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8
bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device
offers access times to 55 ns with power dissipation of just 220 mW. When the device
is deselected, the CMOS standby current is less than 100 µA.
The AT28HC64BF is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 64-byte page register to allow
writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to
64 bytes of data are internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the device will automatically write
the latched data using an internal control timer. The end of a write cycle can be
detected by DATA polling of I/O7. Once the end of a write cycle has been detected, a
new access for a read or write can begin.
Atmel’s AT28HC64BF has additional features to ensure high quality and manufactura-
bility. The device utilizes internal error correction for extended endurance and
improved data retention characteristics. An optional software data protection mecha-
nism is available to guard against inadvertent writes. The device also includes an
extra 64 bytes of EEPROM for device identification or tracking.
Fast Read Access Time – 70 ns
Automatic Page Write Operation
Fast Write Cycle Times
Low Power Dissipation
Hardware and Software Data Protection
DATA Polling and Toggle Bit for End of Write Detection
High Reliability CMOS Technology
Single 5 V ±10% Supply
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-wide Pinout
Industrial Temperature Ranges
Green (Pb/Halide-free) Packaging Only
– Internal Address and Data Latches for 64 Bytes
– Page Write Cycle Time: 2 ms Maximum (Standard)
– 1 to 64-byte Page Write Operation
– 40 mA Active Current
– 100 µA CMOS Standby Current
– Endurance: 100,000 Cycles
– Data Retention: 10 Years
64K (8K x 8)
High Speed
Parallel
EEPROM with
Page Write and
Software Data
Protection
AT28HC64BF
3648B–PEEPR–4/09

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AT28HC64BF-12PU Summary of contents

Page 1

... When the device is deselected, the CMOS standby current is less than 100 µA. The AT28HC64BF is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing bytes simultaneously ...

Page 2

... I/O0 - I/O7 Data Inputs/Outputs NC No Connect DC Don’t Connect 2.1 28-lead SOIC Top View A12 GND 14 15 AT28HC64BF 2 2.2 32-lead PLCC Top View Note: PLCC package pins 1 and 17 are Don’t Connect. VCC A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/ A11 A10 ...

Page 3

... Read The AT28HC64BF is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high-impedance state when either high. This dual line control gives designers flexibility in preventing bus contention in their systems ...

Page 4

... AT28HC64BF will be protected against inadvertent writes. It should be noted that even after SDP is enabled, the user may still perform a byte or page write to the AT28HC64BF. This is done by preceding the data to be written by the same 3-byte command sequence used to enable SDP ...

Page 5

... MHz OUT -400 µA OH AT28HC64BF-120 -40°C - 85° ±10 High High Z V High Z IL Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any ...

Page 6

... AT28HC64BF-70 AT28HC64BF-90 Min Max Min (1)(2)(3)(4) ADDRESS VALID ACC HIGH after the address transition without impact on t ACC after the falling edge of CE without impact pF). L AT28HC64BF-120 Max Min Max 90 120 90 120 OUTPUT VALID . ACC after an address change CE ACC OE Units ...

Page 7

Input Test Waveforms and Measurement Level 12. Output Test Load 13. Pin Capacitance ( MHz 25°C Symbol Typ OUT Note: 1. This parameter is characterized and is not 100% ...

Page 8

... Chip Select Setup Time CS t Chip Select Hold Time CH t Write Pulse Width ( Data Setup Time Data, OE Hold Time DH OEH 15. AC Write Waveforms 15.1 WE Controlled OE ADDRESS CE WE DATA IN 15.2 CE Controlled OE ADDRESS WE CE DATA IN AT28HC64BF 8 t OES t OEH OES Min Max ...

Page 9

Page Mode Characteristics Symbol Parameter t Write Cycle Time WC t Address Setup Time AS t Address Hold Time AH t Data Setup Time DS t Data Hold Time DH t Write Pulse Width WP t Byte Load Cycle ...

Page 10

... A6 - A12 DATA Notes through A12 must specify the same page address during each high to low transition of WE (or CE) after the software code has been entered must be high only when WE and CE are both low. AT28HC64BF 10 20. Software Data Protection Disable Algorithm (2) Notes: ...

Page 11

Data Polling Characteristics Symbol Parameter t Data Hold Time Hold Time OEH ( Output Delay OE t Write Recovery Time WR Note: 1. These parameters are characterized and not 100% tested. 23. Data ...

Page 12

... Normalized I Graphs CC AT28HC64BF 12 3648B–PEEPR–4/09 ...

Page 13

... Contact Atmel Sales in regards to die and wafer sales. 32J 32-lead, Plastic J-leaded Chip Carrier (PLCC) 28S 28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 3648B–PEEPR–4/09 Ordering Code Package AT28HC64BF-12JU AT28HC64BF-12SU Package Type Operation Range 32J Industrial 28S (-40°C to 85°C) 13 ...

Page 14

... Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT28HC64BF 14 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER E1 E ...

Page 15

SOIC Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. 2325 Orchard Parkway San Jose, CA 95131 R 3648B–PEEPR–4/09 0.51(0.020) 0.33(0.013) 7.60(0.2992) 7.40(0.2914) PIN 1 1.27(0.50) BSC TOP VIEW 18.10(0.7125) 17.70(0.6969) 0.30(0.0118) 0.10(0.0040) 0º ~ 8º 1.27(0.050) 0.40(0.016) ...

Page 16

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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