AT28HC64BF-12PU Atmel, AT28HC64BF-12PU Datasheet - Page 4

• Manufacturer Part Number: AT28HC64BF-12PU
• Description: IC EEPROM 64KBIT 120NS 28DIP
• Manufacturer: Atmel

Specifications of AT28HC64BF-12PU

• Format - Memory: EEPROMs - Parallel
• Memory Type: EEPROM
• Memory Size: 64K (8K x 8)
• Speed: 120ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.5
4.6
4.6.1
4.6.2
4.7
4
Toggle Bit
Data Protection
Device Identification
AT28HC64BF
Hardware Protection
Software Data Protection
In addition to DATA Polling, the AT28HC64BF provides another method for determining the end
of a write cycle. During the write operation, successive attempts to read data from the device will
result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop tog-
gling, and valid data will be read. Toggle bit reading may begin at any time during the write cycle.
If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel
memory against inadvertent writes.
Hardware features protect against inadvertent writes to the AT28HC64BF in the following ways:
(a) V
delay – once V
allowing a write; (c) write inhibit – holding any one of OE low, CE high or WE high inhibits write
cycles; and (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not ini-
tiate a write cycle.
A software-controlled data protection feature has been implemented on the AT28HC64BF.
When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP fea-
ture may be enabled or disabled by the user; the AT28HC64BF is shipped from Atmel with SDP
disabled.
SDP is enabled by the user issuing a series of three write commands in which three specific
bytes of data are written to three specific addresses (refer to the “Software Data Protection Algo-
rithm” diagram on
entire AT28HC64BF will be protected against inadvertent writes. It should be noted that even
after SDP is enabled, the user may still perform a byte or page write to the AT28HC64BF. This is
done by preceding the data to be written by the same 3-byte command sequence used to enable
SDP.
Once set, SDP remains active unless the disable command sequence is issued. Power transi-
tions do not disable SDP, and SDP protects the AT28HC64BF during power-up and power-
down conditions. All command sequences must conform to the page write timing specifications.
The data in the enable and disable command sequences is not actually written into the device;
their addresses may still be written with user data in either a byte or page write operation.
After setting SDP, any attempt to write to the device without the 3-byte command sequence will
start the internal write timers. No data will be written to the device, however. For the duration of
t
An extra 64 bytes of EEPROM memory are available to the user for device identification. By rais-
ing A9 to 12 V ±0.5 V and using address locations 1FC0H to 1FFFH, the additional bytes may
be written to or read from in the same manner as the regular memory array.
WC
, read operations will effectively be polling operations.
CC
sense – if V
CC
has reached 3.8 V, the device will automatically time out 5 ms (typical) before
page
®
CC
has incorporated both hardware and software features that will protect the
is below 3.8 V (typical), the write function is inhibited; (b) V
10). After writing the 3-byte command sequence and waiting t
3648B–PEEPR–4/09
CC
power-on
WC
, the