IS42S16100C1-7BLI-TR ISSI, Integrated Silicon Solution Inc, IS42S16100C1-7BLI-TR Datasheet - Page 29
![no-image](/images/manufacturer_photos/0/3/347/issi__integrated_silicon_solution_inc_sml.jpg)
IS42S16100C1-7BLI-TR
Manufacturer Part Number
IS42S16100C1-7BLI-TR
Description
IC SDRAM 16MBIT 143MHZ 60BGA
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet
1.IS42S16100C1-7TL.pdf
(81 pages)
Specifications of IS42S16100C1-7BLI-TR
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
16M (1M x 16)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
60-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS42S16100C1-7BLI-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
IS42S16100C1
CAS latency = 3, burstlength = 4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
08/24/09
Interval Between Write and Read Commands
A new read command can be executed while a write cycle
is in progress, i.e., before that cycle completes. Data
corresponding to the new read command is output after
the CAS latency has elapsed from the point the new read
command was executed. The I/On pins must be placed in
the HIGH impedance state at least one cycle before data
is output during this operation.
CAS latency = 2, burstlength = 4
COMMAND
COMMAND
CLK
CLK
DQ
DQ
WRITE (CA=A, BANK 0)
WRITE (CA=A, BANK 0)
D
D
WRITE A0 READ B0
WRITE A0 READ B0
IN
IN
A0
A0
t
t
CCD
CCD
READ (CA=B, BANK 0)
READ (CA=B, BANK 0)
HI-Z
D
OUT
HI-Z
B0
The interval (t
one clock cycle.
The selected bank must be set to the active state before
executing this command.
D
D
OUT
OUT
B0
B1
D
D
OUT
OUT
ccd
B2
B1
) between command must be at least
D
D
OUT
OUT
B2
B3
D
OUT
B3
29