CY7C131-15JC Cypress Semiconductor Corp, CY7C131-15JC Datasheet - Page 7

• Manufacturer Part Number: CY7C131-15JC
• Description: IC SRAM 8KBIT 15NS 52PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C131-15JC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 8K (1K x 8)
• Speed: 15ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 52-PLCC
• Density: 8Kb
• Access Time (max): 15ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 10b
• Package Type: PLCC
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 190mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 52
• Word Size: 8b
• Number Of Words: 1K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1192

Switching Waveforms
Notes:
Read Cycle No. 2
Read Cycle No.3
Write Cycle No.1 (OE Three-States Data I/Os - Either Port)
ADDRESS
21. Address valid prior to or coincident with CE transition LOW.
22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
ADDRESS
ADDRESS
DATA
D
DATA OUT
OUT
to be placed on the bus for the required t
R/W
DOUT
BUSY
OE
CE
IN
R/W
D
INR
I
OE
I
CE
CC
SB
R
L
L
R
L
[20]
[19, 21]
t
PU
t
HZOE
(continued)
t
LZCE
t
SD
SA
.
Read with BUSY, Master: CY7C130 and CY7C131
t
LZOE
t
PS
t
ACE
t
t
BLA
t
Either Port CE/OE Access
DOE
SCE
ADDRESS MATCH
t
AW
Either Port
t
WC
t
RC
7
[15, 22]
HIGH IMPEDANCE
t
PWE
ADDRESS MATCH
PWE
DATA VALID
t
PWE
t
SD
or t
HZWE
DATA VALID
t
WDD
VALID
+ t
SD
to allow the data I/O pins to enter high impedance and for data
t
t
DDD
HZOE
t
t
HD
BHA
t
t
HA
CY7C130/CY7C131
CY7C140/CY7C141
HD
t
HZCE
t
BDD
t
PD
VALID
C130-9
C130-10
C130-8