RC28F256K3C120 NUMONYX, RC28F256K3C120 Datasheet - Page 36

• Manufacturer Part Number: RC28F256K3C120
• Description: IC FLASH 256MBIT 120NS 64BGA
• Manufacturer: NUMONYX

Specifications of RC28F256K3C120

• Rohs Status: RoHS non-compliant
• Format - Memory: FLASH
• Memory Type: StrataFlash® FLASH
• Memory Size: 256M (16Mx16)
• Speed: 120ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-BGA
• Other names: 853157

28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
9.1.2
9.1.3
9.1.4
9.1.5
36
Note: If RST# is asserted during a program or erase operation, the operation will be aborted and the
Write/Program
To perform a bus write operation, both CE# and WE# are asserted, and OE# is de-asserted. All
device write operations are asynchronous, with CLK being ignored. During a write operation,
address and data are latched on the rising edge of WE# or CE#, whichever occurs first. See
Table 15, “Command Bus Definitions” on page 37
“Write Operation” on page
Write operations with invalid V
not be attempted.
Output Disable
When OE# is de-asserted, device outputs, D[15:0], are disabled and placed in a high-impedance
state.
Standby
When CE# is de-asserted, the device is deselected and placed in standby, substantially reducing
power consumption. In standby, the data outputs are placed in a high-impedance state independent
of the level placed on OE#. If the device is de-selected (CE# de-asserted) during a program or erase
operation, it will continue to consume active power until the program or erase operation is
completed. There is no additional latency for subsequent read operations.
Reset
After initial power-up or reset, the device defaults to Read Array mode and the device status
register is set to 0x80. If already in Read Array mode, asserting RST# de-energizes all internal
circuits, and places the output drivers in a high-impedance state. After returning from reset (RST#
de-asserted) a minimum amount of time is required before the initial read access outputs valid data.
Also, a minimum delay is required after a reset before a write cycle can be initiated. After this
wake-up interval has passed, normal operation is restored. See
page 24
memory contents at the aborted location (for a program) or block (for an erase) are no longer valid,
since the data may have been only partially written or erased.
When RST# is asserted, the device shuts down the operation in progress, a process which takes a
minimum amount of time to complete. When RST# has been de-asserted, the device will be reset to
read array mode. If the system is returning from an aborted program or erase operation, a minimum
amount of time must be satisfied before a read or write operation is initiated.
As with any automated device, it is important to assert RST# when the system is reset. When the
system comes out of reset, the system processor will attempt to read from the flash memory if it is
the system boot device. Automated flash memories provide status information when read during
program or block erase operations. If a CPU reset occurs with no flash memory reset, improper
CPU initialization may occur because the flash memory may be providing status information rather
than array data. Intel
reset through the use of the RST# input. RST# should be controlled by the same low-true reset
signal that resets the system CPU.
for reset timing details.
®
Flash memory devices allow proper CPU initialization following a system
29.
CC
and/or V
PEN
voltages can produce spurious results and should
for bus cycle commands. See
Section 7.1, “Read Operations” on
Section 7.2,
Datasheet