RC28F256K3C120 NUMONYX, RC28F256K3C120 Datasheet - Page 58

• Manufacturer Part Number: RC28F256K3C120
• Description: IC FLASH 256MBIT 120NS 64BGA
• Manufacturer: NUMONYX

Specifications of RC28F256K3C120

• Rohs Status: RoHS non-compliant
• Format - Memory: FLASH
• Memory Type: StrataFlash® FLASH
• Memory Size: 256M (16Mx16)
• Speed: 120ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-BGA
• Other names: 853157

28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
14.3
14.4
58
Table 22. STS Configuration Coding Definitions
Read Query/CFI
The query register contains an assortment of flash product information such as block size, density,
allowable command sets, electrical specifications and other product information. The data
contained in this register conforms to the Common Flash Interface (CFI) protocol. To obtain any
information from the query register, execute the Read Query Register command. See
“Device Commands” on page 37
Appendix B, “Common Flash Interface” on page 64
Information contained in this register can only be accessed by executing a single-word read.
STS Configuration (Easy BGA package ONLY)
To configure the STS signal, execute the Configuration command. The STS signal can be
configured for level or pulse mode. Once configured to a particular mode, it remains in that mode
until the device is powered down, reset or another Configuration command is issued to change the
mode. After power-up or reset, the default configuration is level mode. Level mode works similar
to a Ready/Busy signal (RY/BY#), indicating the status of the Write State Machine (WSM) during
a program or erase operation. The STS Configuration command may only be given when the
device is not busy or suspended. The possible STS configurations and usage are described in
22.
DQ
00 = default, level mode;
01 = pulse on Erase Complete
10 = pulse on Program Complete
11 = pulse on Erase or Program
NOTES:
1. When configured in one of the pulse modes, STS pulses low with a typical pulse width of 250 ns.
2. An invalid configuration code will result in both status register bits SR.4 and SR.5 being set.
1–
DQ7
device ready indication
Complete
DQ
0
= STS Configuration Codes
DQ6
DQ5
Reserved
for details on issuing the CFI Query command. Refer to
Used to control HOLD to a memory controller to prevent accessing a
flash memory subsystem while any flash device's WSM is busy.
Used to generate a system interrupt pulse when any flash device in
an array has completed a block erase. Helpful for reformatting blocks
after file system free space reclamation or “cleanup.”
Used to generate a system interrupt pulse when any flash device in
an array has completed a program operation. Provides highest
performance for servicing continuous buffer write operations.
Used to generate system interrupts to trigger servicing of flash arrays
when either erase or program operations are completed, when a
common interrupt service routine is desired.
DQ4
for a detailed explanation of the CFI register.
DQ3
Notes
DQ2
Complete
Pulse on
Program
DQ1
(1)
Section 9.2,
Datasheet
Complete
Pulse on
Erase
DQ0
(1)
Table