M25P05-AVMN6T NUMONYX, M25P05-AVMN6T Datasheet - Page 15

• Manufacturer Part Number: M25P05-AVMN6T
• Description: IC FLASH 512KBIT 40MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P05-AVMN6T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 512K (64K x 8)
• Speed: 40MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-1621-2

Read Status Register (RDSR)
The Read Status Register (RDSR) instruction al-
lows the Status Register to be read. The Status
Register may be read at any time, even while a
Program, Erase or Write Status Register cycle is in
progress. When one of these cycles is in progress,
it is recommended to check the Write In Progress
(WIP) bit before sending a new instruction to the
device. It is also possible to read the Status Reg-
ister continuously, as shown in
Table 6. Status Register Format
The status and control bits of the Status Register
are as follows:
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1,
such a cycle is in progress, when reset to 0 no
such cycle is in progress.
Figure 11. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence
Status Register Write Protect
SRWD
b7
S
C
D
Q
0
0
Block Protect Bits
0
Write Enable Latch Bit
High Impedance
0
1
2
BP1
Instruction
Write In Progress Bit
3
Figure 11.
4
BP0
5
6
WEL
7
MSB
7
8
WIP
6
b0
Status Register Out
9 10 11 12 13 14 15
5
4
3
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, when set to 0 the internal Write Enable Latch
is reset and no Write Status Register, Program or
Erase instruction is accepted.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Program and Erase
instructions. These bits are written with the Write
Status Register (WRSR) instruction. When one or
both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in
2.) becomes protected against Page Program
(PP) and Sector Erase (SE) instructions. The
Block Protect (BP1, BP0) bits can be written pro-
vided that the Hardware Protected mode has not
been set. The Bulk Erase (BE) instruction is exe-
cuted if, and only if, both Block Protect (BP1, BP0)
bits are 0.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode (when the Status Register Write
Disable (SRWD) bit is set to 1, and Write Protect
(W) is driven Low). In this mode, the non-volatile
bits of the Status Register (SRWD, BP1, BP0) be-
come read-only bits and the Write Status Register
(WRSR) instruction is no longer accepted for exe-
cution.
2
1
0
MSB
7
6
Status Register Out
5
4
3
2
1
0
7
AI02031E
M25P05-A
Table
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