M25P05-AVMN6T NUMONYX, M25P05-AVMN6T Datasheet - Page 19
![no-image](/images/manufacturer_photos/0/4/484/numonyx_sml.jpg)
M25P05-AVMN6T
Manufacturer Part Number
M25P05-AVMN6T
Description
IC FLASH 512KBIT 40MHZ 8SOIC
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.M25P05-AVMN6T.pdf
(42 pages)
Specifications of M25P05-AVMN6T
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
512K (64K x 8)
Speed
40MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
497-1621-2
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25P05-AVMN6TP
Manufacturer:
FREESCALE
Quantity:
110
Company:
Part Number:
M25P05-AVMN6TP
Manufacturer:
NUMONYX
Quantity:
2 350
Part Number:
M25P05-AVMN6TP
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
M25P05-AVMN6TP(25P05VP)
Manufacturer:
TI
Quantity:
13
Read Data Bytes at Higher Speed
(FAST_READ)
The device is first selected by driving Chip Select
(S) Low. The instruction code for the Read Data
Bytes at Higher Speed (FAST_READ) instruction
is followed by a 3-byte address (A23-A0) and a
dummy byte, each bit being latched-in during the
rising edge of Serial Clock (C). Then the memory
contents, at that address, is shifted out on Serial
Data Output (Q), each bit being shifted out, at a
maximum frequency f
Serial Clock (C).
The instruction sequence is shown in
The first byte addressed can be at any location.
The address is automatically incremented to the
Figure 14. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence
and Data-Out Sequence
Note: 1. Address bits A23 to A16 must be set to 00h.
S
C
D
Q
S
C
D
Q
0
7
32 33 34
1
High Impedance
C
6
2
, during the falling edge of
Instruction
Dummy Byte
5
3
4
4
35
3
36 37 38 39 40 41 42 43 44 45 46
5
2
6
1
7
Figure 14.
23
0
8
MSB
22 21
7
9 10
24 BIT ADDRESS
6
DATA OUT 1
5
3
28 29 30 31
4
2
3
next higher address after each byte of data is shift-
ed out. The whole memory can, therefore, be read
with a single Read Data Bytes at Higher Speed
(FAST_READ) instruction.
There is no address roll-over; when the highest
address (0FFFFh) is reached, the instruction
should be terminated.
The
(FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driv-
en High at any time during data output. Any Read
Data Bytes at Higher Speed (FAST_READ) in-
struction, while an Erase, Program or Write cycle
is in progress, is rejected without having any ef-
fects on the cycle that is in progress.
1
2
0
1
Read
0
47
MSB
7
Data
6
DATA OUT 2
5
4
Bytes
3
2
1
at
0
MSB
Higher
7
M25P05-A
AI04006
Speed
19/42