PSD834F2-70J STMicroelectronics, PSD834F2-70J Datasheet - Page 92
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PSD834F2-70J
Manufacturer Part Number
PSD834F2-70J
Description
IC FLASH 2MBIT 70NS 52PLCC
Manufacturer
STMicroelectronics
Datasheet
1.PSD813F2VA-20JI.pdf
(109 pages)
Specifications of PSD834F2-70J
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
2M (256K x 8)
Speed
70ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-2004-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PSD834F2-70J
Manufacturer:
WSI
Quantity:
409
Company:
Part Number:
PSD834F2-70J
Manufacturer:
STMicroelectronics
Quantity:
10 000
PSD813F2V, PSD854F2V
Table 58. WRITE Timing (3V devices)
Note: 1. Any input used to select an internal PSD function.
Table 59. Program, WRITE and Erase Times (5V devices)
Note: 1. Programmed to all zero before erase.
92/109
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
LVLX
AVLX
LXAX
AVWL
SLWL
DVWH
WHDX
WLWH
WHAX1
WHAX2
WHPV
DVMV
AVPV
WLMV
WHQV3
WHQV2
WHQV1
WHWLO
Q7VQV
Symbol
2. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
3. WR has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active WRITE signal.
5. Assuming WRITE is active before data becomes valid.
6. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.
ALE or AS Pulse Width
Address Setup Time
Address Hold Time
Address Valid to Leading
Edge of WR
CS Valid to Leading Edge of WR
WR Data Setup Time
WR Data Hold Time
WR Pulse Width
Trailing Edge of WR to Address Invalid
Trailing Edge of WR to DPLD Address
Invalid
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
Data Valid to Port Output Valid
Using Macrocell Register Preset/Clear
Address Input Valid to Address
Output Delay
WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear
Flash Program
Flash Bulk Erase
Flash Bulk Erase (not pre-programmed)
Sector Erase (pre-programmed)
Sector Erase (not pre-programmed)
Byte Program
Program / Erase Cycles (per Sector)
Sector Erase Time-Out
DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)
Parameter
1
(pre-programmed)
Parameter
Doc ID 10552 Rev 3
Conditions
(Notes
(Notes
(Notes
(Note
(Note
(Note
(Note
(Note
(Note
(Note
(Note
(Note
(Note
3,6
1,3
3,5
3,4
1
1
3
3
3
3
3
3
2
)
)
)
)
)
)
)
)
)
2
)
)
)
)
100,000
Min Max Min Max Min Max
26
17
17
45
46
10
Min.
9
9
7
0
-12
33
70
33
70
26
10
12
20
20
45
48
12
Typ.
100
8
0
8.5
2.2
14
3
5
1
-15
35
70
35
70
Max.
1200
30
12
14
25
25
50
10
53
17
30
30
30
0
-20
40
80
40
80
cycles
Unit
µs
ns
µs
s
s
s
s
s
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns