CY7C1361B-117AC Cypress Semiconductor Corp, CY7C1361B-117AC Datasheet - Page 8

• Manufacturer Part Number: CY7C1361B-117AC
• Description: IC SRAM 9MBIT 117MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1361B-117AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 117MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1505

Document #: 38-05302 Rev. *B
CY7C1361B–Pin Definitions
ADSC
BWE
ZZ
DQ
DQP
MODE
V
V
DD
DDQ
Name
s
[A:D]
52,53,56,57,
58,59,62,63,
68,69,72,73,
74,75,78,79,
12,13,18,19,
22,23,24,25,
15,41,65,91 15,41,65,91 J2,C4,J4,
54,61,70,77
2,3,6,7,8,9,
4,11,20,27,
51,80,1,30
Enable)
(3-Chip
TQFP
28,29
85
87
64
31
52,53,56,57,
58,59,62,63,
68,69,72,73,
74,75,78,79,
12,13,18,19,
22,23,24,25,
54,61,70,77
2,3,6,7,8,9,
4,11,20,27,
51,80,1,30 P6,D6,D2,
Enable)
(2-Chip
TQFP
28,29
85
87
64
31
(continued)
F6,G6,H6,
D7,E7,G7,
H7,D1,E1,
G1,H1,E2,
F2,G2,H2,
K6,L6,M6,
N7,P7,E6,
N6,K7,L7,
K1,L1,N1,
P1,K2,L2,
A1,F1,J1,
A7,F7,J7,
Enable)
(2-Chip
M1,U1,
M2,N2
M7,U7
R4,J6
BGA
M4
B4
P2
R3
T7
N11,C11,C1,
G1,D2,E2,
C3,C9,D3,
L9,M3,M9,
K1,L1,M1,
D4,D8,E4,
D9,E3,E9,
D1,E1,F1,
H4,H8,J4,
L4,L8,M4,
F3,F9,G3,
F2,G2,J1,
E8,F4,F8,
J8,K4,K8,
G9,J3,J9,
K3,K9,L3,
L10,M10,
D10,E10,
F10,G10,
M11,L11,
D11,E11,
F11,G11,
J10,K10,
J2,K2,L2
K11,J11,
Enable)
(3-Chip
G4,G8,
N3,N9
fBGA
H11
M2,
M8
N1
R1
A8
A7
Asynchronous
Power Supply Power supply inputs to the core of the
Synchronous
Synchronous
Synchronous
Synchronous
Input-Static
I/O Power
Supply
Input-
Input-
Input-
I/O-
I/O-
I/O
Address Strobe from Controller, sampled
on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented
to the device are captured in the address
registers. A[1:0] are also loaded into the
burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized.
Byte Write Enable Input, active LOW.
Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a
byte write.
ZZ “sleep” Input, active HIGH. When
asserted HIGH places the device in a
non-time-critical “sleep” condition with data
integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin
has an internal pull-down.
Bidirectional Data I/O lines. As inputs, they
feed into an on-chip data register that is
triggered by the rising edge of CLK. As
outputs, they deliver the data contained in
the memory location specified by the
addresses presented during the previous
clock rise of the read cycle. The direction of
the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs.
When HIGH, DQ
in a three-state condition. The outputs are
automatically three-stated during the data
portion of a write sequence, during the first
clock when emerging from a deselected
state, and when the device is deselected,
regardless of the state of OE.
Bidirectional Data Parity I/O Lines.
Functionally, these signals are identical to
DQ
controlled by BW
Selects Burst Order. When tied to GND
selects linear burst sequence. When tied to
V
sequence. This is a strap pin and should
remain static during device operation. Mode
Pin has an internal pull-up.
device.
Power supply for the I/O circuitry.
DD
s
. During write sequences, DQP
or left floating selects interleaved burst
Description
s
[A:D]
and DQP
correspondingly.
CY7C1361B
CY7C1363B
[A:D]
Page 8 of 34
are placed
[A:D]
is