M25P40-VMN6P NUMONYX, M25P40-VMN6P Datasheet - Page 10
![IC FLASH 4MBIT 50MHZ 8SOIC](/photos/7/30/73033/m25p40-vmn6p_sml.jpg)
M25P40-VMN6P
Manufacturer Part Number
M25P40-VMN6P
Description
IC FLASH 4MBIT 50MHZ 8SOIC
Manufacturer
NUMONYX
Series
Forté™r
Specifications of M25P40-VMN6P
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
4M (512K x 8)
Speed
50MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Memory Configuration
512K X 8
Ic Interface Type
Serial, SPI
Clock Frequency
50MHz
Supply Voltage Range
2.3V To 3.6V
Memory Case Style
SOIC
No. Of Pins
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-3598
497-3598
497-3598
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M25P40-VMN6P
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
M25P40-VMN6PB
Manufacturer:
ST
Quantity:
102
Part Number:
M25P40-VMN6PB
Manufacturer:
ST
Quantity:
20 000
Part Number:
M25P40-VMN6PBA
Manufacturer:
MICRON
Quantity:
20 000
3
10/59
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in
bus master is in Standby mode and not transferring data:
Figure 4.
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 4
one device is selected at a time, so only one device drives the Serial Data output (Q) line at
a time, the other devices are high impedance. Resistors R (represented in
that the M25P16 is not selected if the Bus Master leaves the S line in the high impedance
state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at
the same time (for example, when the Bus Master is reset), the clock line (C) must be
connected to an external pull-down resistor so that, when all inputs/outputs become high
impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and
C do not become High at the same time, and so, that the t
typical value of R is 100 k Ω, assuming that the time constant R*C
capacitance of the bus line) is shorter than the time during which the Bus Master leaves the
SPI bus in high impedance.
SPI interface with
CS3
(CPOL, CPHA) =
SPI Bus Master
(0, 0) or (1, 1)
CPOL=0, CPHA=0
CPOL=1, CPHA=1
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
CS2 CS1
shows an example of three devices connected to an MCU, on an SPI bus. Only
Bus master and memory devices on the SPI bus
SDO
SDI
SCK
R
R
C Q D
S
SPI memory
device
W
V
CC
HOLD
V
R
SS
C Q D
S
Figure
SPI memory
device
SHCH
W
5, is the clock polarity when the
V
HOLD
CC
requirement is met). The
R
V
p
SS
(C
p
= parasitic
C Q D
S
Figure
SPI memory
device
W
4) ensure
V
CC
HOLD
AI12836b
V
SS
V
V
CC
SS