CY7C1355C-100AXC Cypress Semiconductor Corp, CY7C1355C-100AXC Datasheet - Page 9

• Manufacturer Part Number: CY7C1355C-100AXC
• Description: IC SRAM 9MBIT 100MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1355C-100AXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1628

Document #: 38-05539 Rev. *E
precaution, DQs and DQP
the data portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1355C/CY7C1357C has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four Write operations without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
the initial address, as described in the Single Write Access
section above. When ADV/LD is driven HIGH on the subse-
quent clock rise, the Chip Enables (CE
WE inputs are ignored and the burst counter is incremented.
The correct BW
burst write, in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
for the duration of t
. .
ZZ Mode Electrical Characteristics
Truth Table
I
t
t
t
t
Deselect Cycle
Deselect Cycle
Deselect Cycle
Continue Deselect Cycle
READ Cycle (Begin Burst)
READ Cycle (Continue Burst)
NOP/DUMMY READ (Begin Burst)
DUMMY READ (Continue Burst)
WRITE Cycle (Begin Burst)
WRITE Cycle (Continue Burst)
Notes:
DDZZ
ZZS
ZZREC
ZZI
RZZI
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write
3. Write is defined by BW
4. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
5. The DQs and DQP
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQs and DQP
Parameter
Selects are asserted, see Truth Table for details.
is inactive or when the device is deselected, and DQs and DQP
Operation
[2, 3, 4, 5, 6, 7, 8]
X
inputs must be driven in each cycle of the
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
X
ZZREC
pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
X
1
, and WE. See Truth Table for Read/Write.
, CE
after the ZZ input returns LOW.
X
2
are automatically tri-stated during
, and CE
Description
3
, must remain inactive
1
, CE
Address
External
External
External
Used
None
None
None
None
Next
Next
Next
2
, and CE
CE
H
X
X
X
X
X
X
L
L
L
X
3
= data when OE is active.
1
) and
CE
X
X
X
H
X
H
X
H
X
L
2
CE
ZZ > V
ZZ < 0.2V
ZZ > V
This parameter is sampled
This parameter is sampled
X
H
X
X
X
X
X
L
L
L
3
Interleaved Burst Address Table
(MODE = Floating or VDD)
Linear Burst Address Table (MODE = GND)
ZZ ADV/LD WE BW
Address
Address
Test Conditions
L
L
L
L
L
L
L
L
L
L
A1: A0
A1: A0
DD
DD
First
First
00
01
10
00
01
10
11
11
– 0.2V
– 0.2V
H
H
H
H
L
L
L
L
L
L
Address
Address
Second
Second
X
X
X
X
H
X
H
X
X
L
A1: A0
A1: A0
01
00
11
10
01
10
11
00
X
X
X
X
X
X
X
X
L
L
X
2t
OE CEN CLK
Min.
H
H
X
X
X
X
X
X
L
L
CYC
0
Address
Address
A1: A0
A1: A0
Third
Third
L
L
L
L
L
L
L
L
L
L
10
00
01
10
00
01
11
11
CY7C1355C
CY7C1357C
2t
2t
L->H
L->H
L->H
L->H
L->H Data Out (Q)
L->H Data Out (Q)
L->H
L->H
L->H Data In (D)
L->H Data In (D)
Max.
50
CYC
CYC
X
= Tri-state when OE
Page 9 of 28
Address
Address
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Fourth
A1: A0
Fourth
A1: A0
11
10
01
00
11
00
01
10
DQ
Unit
mA
ns
ns
ns
ns
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