CY7C1381D-133BGXC Cypress Semiconductor Corp, CY7C1381D-133BGXC Datasheet
CY7C1381D-133BGXC
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CY7C1381D-133BGXC Summary of contents
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... Cypress Semiconductor Corporation Document #: 38-05544 Rev. *A PRELIMINARY Functional Description The CY7C1381D/CY7C1383D is a 3.3V, 512K x 36 and 1 Mbit x 18 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with ) minimum glue logic. Maximum access delay from clock rise is DD 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automati- cally for the rest of the burst access ...
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... Logic Block Diagram – CY7C1381D (512K x 36) A0, A1, A MODE ADV CLK ADSC ADSP DQ DQP , BYTE BYTE WRITE REGISTER WRITE REGISTER DQ DQP , BYTE WRITE REGISTER DQ DQP , BYTE WRITE REGISTER DQ DQP , BYTE BWE WRITE REGISTER GW ENABLE CE1 REGISTER CE2 CE3 OE SLEEP ZZ CONTROL 2 Logic Block Diagram – CY7C1383D (1 Mbit x 18) ...
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... TQFP Pinout DQP DDQ 4 DDQ SSQ 5 SSQ SSQ 10 SSQ DDQ 11 DDQ /DNU DDQ 20 DDQ SSQ 21 SSQ DQP SSQ 26 SSQ DDQ 27 DDQ DQP CY7C1381D CY7C1383D DDQ 76 V SSQ DQP SSQ 70 V DDQ CY7C1383D ( DDQ V 60 SSQ SSQ V 54 DDQ Page ...
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... Pin Configurations (continued DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ Document #: 38-05544 Rev. *A PRELIMINARY 119-ball BGA (1 Chip Enable with JTAG) CY7C1381D (512K x 36 ADSP A A ADSC DQP ADV CLK BWE DQP MODE TMS TDI TCK CY7C1383D (1M x 18) ...
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... D D DDQ N DQP DDQ 72M A R MODE NC / 36M 288M DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ 72M A R MODE NC / 36M A Document #: 38-05544 Rev. *A PRELIMINARY 165-ball fBGA (3 Chip Enable) CY7C1381D (512K x 36 CLK TDI TMS CY7C1383D ( CLK ...
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... Selects Burst Order. When tied to GND selects linear burst sequence. When tied left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. Power supply inputs to the core of the device. Ground for the core of the device. CY7C1381D CY7C1383D Description [ and CE are sampled active ...
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... Maximum access delay from the clock rise ( 6.5 ns (133-MHz device). CDV The CY7C1381D/CY7C1383D supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium processors. The linear burst sequence is suited for processors that utilize a linear burst sequence ...
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... ZZ > V – 0. < 0.2V This parameter is sampled This parameter is sampled ADSP CY7C1381D CY7C1383D [ ADSP, and ADSC must after the ZZ input ZZREC Min. Max CYC 2t CYC 2t CYC 0 ADSC ADV WRITE OE CLK L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State L-H Q ...
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... Read Cycle, Suspend Burst Current Read Cycle, Suspend Burst Current Read Cycle, Suspend Burst Current Write Cycle, Suspend Burst Current Write Cycle, Suspend Burst Current Partial Truth Table for Read/Write Function (CY7C1381D) Read Read Write Byte A (DQ , DQP ) A A Write Byte B(DQ , DQP ) ...
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... Write All Bytes Write All Bytes IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1381D/CY7C1383D incorporates a serial boundary scan test access port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but doesn’ ...
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... The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. CY7C1381D CY7C1383D or INTEST or ...
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... Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions CYC TL t TMSS t TMSH t TDIS t TDIH DON’T CARE CY7C1381D CY7C1383D and t ). The SRAM clock input might not TDOV t TDOX UNDEFINED Page ...
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... Input pulse levels SS Input rise and fall time .....................................................1 ns Input timing reference levels......................................... 1.25V Output reference levels ................................................ 1.25V Test load termination supply voltage ............................ 1.25V 2.5V TAP AC Output Load Equivalent 1.5V 50 TDO 20pF /t = 1ns R F CY7C1381D CY7C1383D Min. Max. Unit MHz ...
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... Reserved for Internal Use 000001 000001 Defines memory type and architecture 100101 010101 Defines width and density 00000110100 00000110100 Allows unique identification of SRAM vendor Indicates the presence register. Bit Size (×36 CY7C1381D CY7C1383D Min. Max. Unit 2.4 V 2.0 V 2.9 V 2.1 V 0.4 V 0.4 V 0.2 V ...
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... Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. CY7C1381D CY7C1383D Description Page ...
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... BGA Boundary Scan Order CY7C1381D (256K × 36) Bit# Ball ID Bit Notes: 13. Balls that are NC (No Connect) are Pre-Set LOW. 14. Bit Pre-Set HIGH. Document #: 38-05544 Rev. *A PRELIMINARY [13, 14] Ball ID Bit# Ball Internal 42 43 CY7C1381D CY7C1383D CY7C1383D (512K × 18) Bit# Ball ID 44 ...
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... BGA Boundary Scan Order CY7C1381D (256K x 36) Bit# Ball ID Bit 10N 39 4 P11 P10 45 10 R10 46 11 R11 47 12 H11 48 13 N11 49 14 M11 50 15 L11 51 16 K11 52 17 J11 53 18 M10 54 19 L10 55 20 K10 56 21 J10 H10 59 24 ...
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... G11 60 25 F11 61 26 E11 62 27 D11 63 28 G10 64 29 F10 65 30 E10 66 31 D10 67 32 C11 68 33 A11 69 34 B11 70 35 A10 71 36 B10 72 Document #: 38-05544 Rev. *A PRELIMINARY [13, 15] CY7C1383D (512Kx18) Ball ID Bit C10 CY7C1381D CY7C1383D Ball Internal Page ...
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... V – 0. inputs static /2), undershoot: V (AC) > -2V (Pulse width less than t CYC IL (min.) within 200ms. During this time V < CY7C1381D CY7C1383D Ambient Temperature V DD 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5% –40°C to +85°C Min. Max. 3.135 3.6 3.135 ...
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... OUTPUT =1538Ω INCLUDING JIG AND (b) SCOPE [20, 21] Description Min. [19] 1 7.5 2.1 2.1 2.0 [20, 21, 22] 2.0 [20, 21, 22] 0 [20, 21, 22] 0 [20, 21, 22] 1.5 CY7C1381D CY7C1383D BGA Package fBGA Package ALL INPUT PULSES V DDQ 90% 10% GND ≤ 1ns (c) ALL INPUT PULSES ...
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... V POWER is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ CY7C1381D CY7C1383D 133 MHz 100 MHz Max. Min. Max. 1.5 1.5 1.5 1 ...
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... This parameter is sampled and not 100% tested. Document #: 38-05544 Rev. *A PRELIMINARY t ADS t ADH ADVH ADVS ADV suspends burst t CDV t OELZ t OEHZ t DOH Q(A2 DON’T CARE CY7C1381D CY7C1383D Deselect Cycle Q( Q(A2) Q( Burst wraps around to its initial state BURST READ UNDEFINED Page CHZ Q( ...
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... Test conditions shown in ( Test Loads unless otherwise noted. Document #: 38-05544 Rev. *A PRELIMINARY ADSC extends burst WEH WES ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED = 2.5V. DDQ CY7C1381D CY7C1383D t ADS t ADH A3 t WES t WEH t ADVS t ADVH D( D(A3 Extended BURST WRITE Page ...
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... GW is HIGH. Document #: 38-05544 Rev. *A PRELIMINARY WES WEH OELZ D(A3) t OEHZ t CDV Q(A4) Single WRITE DON’T CARE is HIGH and CE is LOW. When CE is HIGH LOW. X CY7C1381D CY7C1383D A5 D(A5) Q(A4+1) Q(A4+2) Q(A4+3) Back-to-Back BURST READ WRITEs UNDEFINED is HIGH LOW HIGH Page D(A6) ...
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... I SUPPLY ALL INPUTS (except ZZ) Outputs (Q) Ordering Information Speed (MHz) Ordering Code 133 CY7C1381D-133AXC CY7C1383D-133AXC CY7C1381D-133BGC CY7C1383D-133BGC CY7C1381D-133BZC CY7C1383D-133BZC CY7C1381D-133BGXC CY7C1383D-133BGXC CY7C1381D-133BZXC CY7C1383D-133BZXC 100 CY7C1381D-100AXC CY7C1383D-100AXC CY7C1381D-100BGC CY7C1383D-100BGC CY7C1381D-100BZC CY7C1383D-100BZC CY7C1381D-100BGXC CY7C1383D-100BGXC CY7C1381D-100BZXC CY7C1383D-100BZXC Notes: 29. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. ...
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... CY7C1381D-100BGI CY7C1383D-100BGI CY7C1381D-100BZI CY7C1383D-100BZI CY7C1381D-100BGXI CY7C1383D-100BGXI CY7C1381D-100BZXI CY7C1383D-100BZXI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Lead-free BG packages (ordering Code:BGX) will be available in 2005. Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 16.00±0.20 14.00± ...
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... Package Diagrams (continued) Document #: 38-05544 Rev. *A PRELIMINARY 119-Lead PBGA ( 2.4 mm) BG119 CY7C1381D CY7C1383D 51-85115-*B Page ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY 165 FBGA 1.40 MM BB165D CY7C1381D CY7C1383D 51-85180-** Page ...
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... Document History Page Document Title: CY7C1381D/CY7C1383D 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM Document Number: 38-05544 REV. ECN NO. Issue Date ** 254518 See ECN *A 288531 See ECN Document #: 38-05544 Rev. *A PRELIMINARY Orig. of Change Description of Change RKF New data sheet SYT Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for non-compliance with 1149 ...