CY7C1270V18-375BZC Cypress Semiconductor Corp, CY7C1270V18-375BZC Datasheet - Page 19
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CY7C1270V18-375BZC
Manufacturer Part Number
CY7C1270V18-375BZC
Description
IC SRAM 36MBIT 375MHZ 165TFBGA
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C1268V18-400BZXC.pdf
(27 pages)
Specifications of CY7C1270V18-375BZC
Format - Memory
RAM
Memory Type
SRAM - Synchronous, DDR II
Memory Size
36M (1M x 36)
Speed
375MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 70°C
Package / Case
165-TFBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C1270V18-375BZC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Power Up Sequence in DDR-II+ SRAM
DDR-II+ SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations. During
power up, when the DOFF is tied HIGH, the DLL gets locked after
2048 cycles of stable clock.
Power Up Sequence
■
■
Power Up Waveforms
Document Number: 001-06347 Rev. *D
Apply power with DOFF tied HIGH (all other inputs can be HIGH
or LOW)
❐
❐
Provide stable power and clock (K, K) for 2048 cycles to lock
the DLL
V DD /V DDQ
Apply V
Apply V
DOFF
DD
DDQ
K
K
before V
before V
DDQ
REF
Clock Start (Clock Starts after V DD /V DDQ is Stable)
Unstable Clock
or at the same time as V
V DD /V DDQ Stable (< + 0.1V DC per 50 ns)
Fix HIGH (tie to V DDQ )
Figure 3. Power Up Waveforms
REF
> 2048 Stable Clock
DLL Constraints
■
■
■
DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as t
The DLL functions at frequencies down to 120 MHz.
If the input clock is unstable and the DLL is enabled, then the
DLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 2048 cycles stable clock
to relock to the desired clock frequency.
CY7C1266V18, CY7C1277V18
CY7C1268V18, CY7C1270V18
Start Normal
Operation
KC Var
Page 19 of 27
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