CY7C1270V18-400BZC Cypress Semiconductor Corp, CY7C1270V18-400BZC Datasheet - Page 10
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CY7C1270V18-400BZC
Manufacturer Part Number
CY7C1270V18-400BZC
Description
IC SRAM 36MBIT 400MHZ 165TFBGA
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C1268V18-400BZXC.pdf
(27 pages)
Specifications of CY7C1270V18-400BZC
Format - Memory
RAM
Memory Type
SRAM - Synchronous, DDR II
Memory Size
36M (1M x 36)
Speed
400MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 70°C
Package / Case
165-TFBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C1270V18-400BZC
Manufacturer:
CYPRESS
Quantity:
210
Company:
Part Number:
CY7C1270V18-400BZC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Write Cycle Descriptions
The write cycle description table for CY7C1266V18 and CY7C1268V18 follows.
Write Cycle Descriptions
The write cycle description table for CY7C1277V18 follows.
Note
Document Number: 001-06347 Rev. *D
8. Assumes a write cycle was initiated per the
BWS
NWS
BWS
H
H
H
H
of a write cycle, as long as the setup and hold requirements are met.
L
L
L
L
H
H
L
L
0
0
0
/
BWS
NWS
L-H
L-H
H
H
H
H
L
L
L
L
K
–
–
1
1
/
L–H
L–H
L–H
L–H
K
–
–
–
–
L-H
L-H
K
–
–
L–H During the data portion of a write sequence:
L–H During the data portion of a write sequence:
L–H No data is written into the devices during this portion of a write operation.
L-H During the data portion of a write sequence:
K
–
–
–
–
During the data portion of a write sequence, the single byte (D
During the data portion of a write sequence, the single byte (D
No data is written into the device during this portion of a write operation.
No data is written into the device during this portion of a write operation.
During the data portion of a write sequence:
CY7C1266V18 − both nibbles (D
CY7C1268V18 − both bytes (D
CY7C1266V18 − both nibbles (D
CY7C1268V18 − both bytes (D
During the data portion of a write sequence:
CY7C1266V18 − only the lower nibble (D
CY7C1268V18 − only the lower byte (D
CY7C1266V18 − only the lower nibble (D
CY7C1268V18 − only the lower byte (D
During the data portion of a write sequence:
CY7C1266V18 − only the upper nibble (D
CY7C1268V18 − only the upper byte (D
CY7C1266V18 − only the upper nibble (D
CY7C1268V18 − only the upper byte (D
No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions
tables. NWS
[2, 8]
[17:0]
[17:0]
[7:0]
[7:0]
0
) are written into the device.
) are written into the device.
) are written into the device.
) are written into the device.
, NWS
[8:0]
[8:0]
[17:9]
[17:9]
Comments
[3:0]
[3:0]
[7:4]
[7:4]
1
Comments
, BWS
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
0
, BWS
[2, 8]
CY7C1266V18, CY7C1277V18
CY7C1268V18, CY7C1270V18
1
, BWS
2
[8:0]
[8:0]
, and BWS
) is written into the device.
) is written into the device.
3
can be altered on different portions
[17:9]
[17:9]
[7:4]
[8:0]
[8:0]
[7:4]
[3:0]
[3:0]
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
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