EPCS64SI16N Altera, EPCS64SI16N Datasheet - Page 21

IC CONFIG DEVICE 64MBIT 16-SOIC

EPCS64SI16N

Manufacturer Part Number
EPCS64SI16N
Description
IC CONFIG DEVICE 64MBIT 16-SOIC
Manufacturer
Altera
Series
EPCSr
Datasheet

Specifications of EPCS64SI16N

Programmable Type
In System Programmable
Memory Size
64Mb
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (0.300", 7.50mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1380-5
EPCS64SI16
EPCS64SI16N

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPCS64SI16N
Manufacturer:
ALTERA
Quantity:
1 290
Part Number:
EPCS64SI16N
Manufacturer:
ALTERA
Quantity:
4
Part Number:
EPCS64SI16N
Manufacturer:
ALTERA42
Quantity:
696
Part Number:
EPCS64SI16N
Manufacturer:
ALTERA
Quantity:
6 000
Part Number:
EPCS64SI16N
Manufacturer:
ALTERA
Quantity:
6 000
Part Number:
EPCS64SI16N
Manufacturer:
XILINX
0
Part Number:
EPCS64SI16N
Manufacturer:
ALTERA
0
Part Number:
EPCS64SI16N
Manufacturer:
ALTERA
Quantity:
20 000
Part Number:
EPCS64SI16N
0
Company:
Part Number:
EPCS64SI16N
Quantity:
18
Part Number:
EPCS64SI16NALTERA
Manufacturer:
ALTERA
0
Chapter 3: Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
Serial Configuration Device Memory Access
© December 2009
Altera Corporation
Fast Read Operation
The device is first selected by driving nCS low. The fast read instruction code is
followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in
during the rising edge of DCLK. Then the memory contents, at that address, is shifted
out on DATA, each bit being shifted out, at a maximum frequency of 40 MHz, during
the falling edge of DCLK.
The instruction sequence is shown in
The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out. The
whole memory can, therefore, be read with a single fast read instruction. When the
highest address is reached, the address counter rolls over to 000000h, allowing the
read sequence to be continued indefinitely.
The fast read instruction is terminated by driving nCS high at any time during data
output. Any fast read instruction is rejected during the Erase, Program, or Write
operations without any effect on the operation that is in progress .
Figure 3–12. FAST_READ Operation Timing Diagram
Note to
(1) Address bit A[23] is a don't-care bit in EPCS64. Address bits A[23..21] are don't-care bits in EPCS16. Address
bits A[23..19] are don't-care bits in EPCS4. Address bits A[23..17] are don't-care bits in the EPCS1.
DCLK
DCLK
ASDI
DATA
ASDI
DATA
nCS
nCS
Figure
7
32
3–12:
6
33
5
34
0
Dummy Byte
4
35
1
3
36
2
High Impedance
Operation Code
2
37
3
1
38
4
0
39
5
MSB
7
40
6
6
41
7
Figure
MSB
5
23
42
8
DATA Out 1
4
22
43
9
3
21
44
3–12.
10
24-Bit Address (1)
2
45
Configuration Handbook (Complete Two-Volume Set)
1
46
0
47
3
MSB
28
7
2
29
6
1
30
5
0
DATA Out 2
31
4
3
2
1
0
MSB
7
3–21

Related parts for EPCS64SI16N