AT17N002-10SI Atmel, AT17N002-10SI Datasheet - Page 4
![IC FPGA 2M CONFIG MEM 20SOIC](/photos/6/80/68042/453-20-soic_sml.jpg)
AT17N002-10SI
Manufacturer Part Number
AT17N002-10SI
Description
IC FPGA 2M CONFIG MEM 20SOIC
Manufacturer
Atmel
Datasheet
1.AT17N256-10NC.pdf
(18 pages)
Specifications of AT17N002-10SI
Programmable Type
Serial EEPROM
Memory Size
2Mb
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (0.300", 7.50mm Width)
For Use With
ATDH2225 - CABLE ISP FOR AT17ATDH2200E - CONFIGURATOR PROGRAM BOARD KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Block Diagram
Device Description
4
AT17N256/512/010/002/040
POWER ON
RESET
SER_EN
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) inter-
face directly with the FPGA device control signals. All FPGA devices can control the
entire configuration process and retrieve data from the configuration EEPROM without
requiring an external intelligent controller.
The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the
DATA output pin and enable the address counter. When RESET/OE is driven High, the
configuration EEPROM resets its address counter and tri-states its DATA pin. The CE
pin also controls the output of the AT17N series configurator. If CE is held High after the
RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated.
When OE is subsequently driven Low, the counter and the DATA output pin are
enabled. When RESET/OE is driven High again, the address counter is reset and the
DATA output pin is tri-stated, regardless of the state of CE. Upon power-up, the address
counter is automatically reset.
3020C–CNFG–08/07