XC17S100APD8C Xilinx Inc, XC17S100APD8C Datasheet

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XC17S100APD8C

Manufacturer Part Number
XC17S100APD8C
Description
IC PROM SER 100000 C-TEMP 8-DIP
Manufacturer
Xilinx Inc
Datasheets
1.XC17S15APD8C.pdf (8 pages)
2.XC17S100APD8C.pdf (4 pages)

Specifications of XC17S100APD8C

Programmable Type
OTP
Memory Size
1Mb
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
8-DIP (0.300", 7.62mm)
Capacitance, Input
10 pF
Capacitance, Output
10 pF
Current, Input, Leakage
±10 μA
Current, Operating
15 mA
Current, Output, Leakage
±10
Data Retention
20 yrs.
Density
781216
Interface
Parallel Bus
Memory Type
PROM
Organization
1M×8
Package Type
PDIP
Temperature, Operating
0 to +70 °C
Time, Address Setup
25
Time, Rise
50 ms
Voltage, Input, High
3.3 V
Voltage, Input, Low
0.8 V
Voltage, Output, High
2.4 V
Voltage, Output, Low
0.4 V
Voltage, Supply
3.3 V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

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Price
Company:
BOSTOCK HK LIMITED BOSTOCK HK LIMITED
Part Number:
XC17S100APD8C
Manufacturer:
XILINX
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DS078 (v1.10) June 25, 2007
Features
Introduction
The XC17S00A family of PROMs provide an easy-to-use,
cost-effective method for storing Spartan-II/Spartan-IIE
device configuration bitstreams.
When the Spartan device is in Master Serial mode, it
generates a configuration clock that drives the Spartan
PROM. A short access time after the rising clock edge, data
appears on the PROM DATA output pin that is connected to
the Spartan device D
DS078 (v1.10) June 25, 2007
Product Specification
Notes:
1.
2.
© 2000-2002, 2005, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams for
Spartan™-II/Spartan-IIE FPGA devices
Simple interface to the Spartan device
Programmable reset polarity (active High or active Low)
Low-power CMOS floating gate process
3.3V PROM
Due to the higher configuration bit requirements of the XC2S150E device, an XC17S200A PROM is required to configure this FPGA.
See XC17V00 series configuration PROMs data sheet at:
PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice.
Spartan-II/IIE FPGA
XC2S150E
XC2S100E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
XC2S50E
XC2S100
XC2S150
XC2S200
XC2S15
XC2S30
XC2S50
IN
pin. The Spartan device generates
(1)
R
0
0
5
Configuration Bits
http://direct.xilinx.com/bvdocs/publications/ds073.pdf
www.xilinx.com
1,040,096
1,335,840
1,134,496
1,442,016
1,875,648
2,693,440
3,961,632
197,696
336,768
559,200
781,216
630,048
863,840
Configuration PROMs (XC17S00A)
Spartan-II/Spartan-IIE Family OTP
the appropriate number of clock pulses to complete the
configuration. Once configured, it disables the PROM.
When a Spartan device is in Slave Serial mode, the PROM
and the Spartan device must both be clocked by an
incoming signal.
For device programming, either the Xilinx Alliance or the
Spartan device design file into a standard HEX format which
is then transferred to most commercial PROM programmers.
Available in compact plastic 8-pin DIP, 8-pin VOIC,
20-pin SOIC, or 44-pin VQFP packages
Programming support by leading programmer
manufacturers
Design support using the Xilinx Alliance and
Foundation™ series software packages
Guaranteed 20-year life data retention
Pb-free (RoHS-compliant) packaging available
Compatible Spartan-II/IIE PROM
XC17S100A
XC17S150A
XC17S200A
XC17S100A
XC17S200A
XC17S200A
XC17S300A
XC17V04
XC17V04
XC17S15A
XC17S30A
XC17S50A
XC17S50A
Product Specification
(2)
(2)
1

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XC17S100APD8C Summary of contents

Page 1

R DS078 (v1.10) June 25, 2007 Features Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for Spartan™-II/Spartan-IIE FPGA devices Simple interface to the Spartan device Programmable reset polarity (active High or active Low) Low-power CMOS floating gate ...

Page 2

R Pin Description Pins not listed are no connects. 8-pin PDIP 20-pin (PD8/PDG8) Pin Name SOIC and (SO20) VOIC/TSOP (VO8/VOG8) DATA 1 CLK 2 RESET/OE 3 (OE/RESET GND 18 Pinout Diagrams DATA ...

Page 3

R Controlling PROMs Connecting the Spartan device with the PROM: The DATA output of the PROM drives the D the lead Spartan device. The Master Spartan device CCLK output drives the CLK input of the PROM. The RESET/OE input of ...

Page 4

R Standby Mode The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high-impedance state regardless of the state of the OE input. RESET OE/ RESET CLK Figure 2: Simplified ...

Page 5

R XC17S15A, XC17S30A, XC17S50A, XC17S100A, XC17S150A, XC17S200A, and XC17S300A Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Input voltage with respect to GND IN V Voltage applied to High-Z output TS T Storage temperature (ambient) STG ...

Page 6

R AC Characteristics Over Operating Condition CE RESET/OE CLK T CE DATA Symbol T RESET/OE to Data Delay Data Delay CE T CLK to Data Delay CAC T Data Hold From CE, RESET/OE, or CLK OH ...

Page 7

... XC17S30ASO20C XC17S30APD8I XC17S30AVO8I XC17S30ASO20I DS078 (v1.10) June 25, 2007 Product Specification Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A) XC17S15A VO8 C XC17S50APD8C XC17S50APDG8C XC17S50AVO8C XC17S50AVOG8C XC17S50ASO20C XC17S50APD8I XC17S50AVO8I XC17S50ASO20I XC17S100APD8C XC17S100AVO8C XC17S100AVOG8C XC17S100ASO20C XC17S100APD8I XC17S100AVO8I XC17S100ASO20I www.xilinx.com Operating Range/Processing C=Commercial ( + I=Industrial (T = – + XC17S150APD8C XC17S150AVO8C ...

Page 8

R Marking Information Due to the small size of the PROM package, the complete ordering part number cannot be marked on the package. The XC prefix is deleted and the package code is simplified. Device marking is as follows. Device ...

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