AT17LV512A-10JC Atmel, AT17LV512A-10JC Datasheet - Page 5
![IC CONFIG SEEPROM 512K 20PLCC](/photos/6/80/68044/453-20-plcc_sml.jpg)
AT17LV512A-10JC
Manufacturer Part Number
AT17LV512A-10JC
Description
IC CONFIG SEEPROM 512K 20PLCC
Manufacturer
Atmel
Datasheet
1.AT17LV512A-10JU.pdf
(18 pages)
Specifications of AT17LV512A-10JC
Programmable Type
Serial EEPROM
Memory Size
512kb
Voltage - Supply
3 V ~ 3.6 V, 4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Package / Case
20-LCC (J-Lead)
Density
512Kb
Interface Type
Serial (2-Wire)
Organization
512Kx1
Frequency (max)
15(Min)MHz
Write Protection
Yes
Data Retention
190Year
Operating Supply Voltage (typ)
3.3/5V
Package Type
PLCC
Operating Temp Range
0C to 70C
Supply Current
10mA
Operating Supply Voltage (min)
3/4.75V
Operating Supply Voltage (max)
3.6/5.25V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
20
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
AT17LV512A10JC
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4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
2322G–CNFG–03/06
DATA
DCLK
WP1
RESET/OE
WP
nCS
GND
nCASC
A2
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
Clock output or clock input. Rising edges on DCLK increment the internal address counter and
present the next bit of data to the DATA pin. The counter is incremented only if the RESET/OE
input is held High, the nCS input is held Low, and all configuration data has not been transferred
to the target device (otherwise, as the master device, the DCLK pin drives Low).
WRITE PROTECT (1). This pin is used to protect portions of memory during programming, and
it is disabled by default due to internal pull-down resistor. This input pin is not used during FPGA
loading operations. This pin is only available on AT17LV512A/010A/002A devices.
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low logic level
resets the address counter. A High logic level (with nCS Low) enables DATA and permits the
address counter to count. In the mode, if this pin is Low (reset), the internal oscillator becomes
inactive and DCLK drives Low. The logic polarity of this input is programmable and must be pro-
grammed active High (RESET active Low) by the user during programming for Altera
applications.
Write protect (WP) input (when nCS is Low) during programming only (SER_EN Low). When
WP is Low, the entire memory can be written. When WP is enabled (High), the lowest block of
the memory cannot be written. This pin is only available on AT17LV65A/128A/256A devices.
Chip Select input (active Low). A Low input (with OE High) allows DCLK to increment the
address counter and enables DATA to drive out. If the AT17A series is reset with nCS Low, the
device initializes as the first (and master) device in a daisy-chain. If the AT17A series is reset
with nCS High, the device initializes as a subsequent AT17A series device in the chain.
Ground pin. A 0.2 µF decoupling capacitor between V
Cascade Select Output (active Low). This output goes Low when the address counter has
reached its maximum value. In a daisy-chain of AT17A series devices, the nCASC pin of one
device is usually connected to the nCS input pin of the next device in the chain, which permits
DCLK from the master configurator to clock data from a subsequent AT17A series device in the
chain. This feature is not available on the AT17LV65A device.
Device selection input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
AT17LV65A/128A/256A/512A/002A
CC
and GND is recommended.
5