XC18V01PC20I Xilinx Inc, XC18V01PC20I Datasheet
XC18V01PC20I
Specifications of XC18V01PC20I
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XC18V01PC20I Summary of contents
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R DS026 (v4.1) December 15, 2003 Features • In-system programmable 3.3V PROMs for configuration of Xilinx FPGAs - Endurance of 20,000 program/erase cycles - Program/erase over full commercial/industrial voltage and temperature range (–40°C to +85°C) • IEEE Std 1149.1 boundary-scan ...
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XC18V00 Series In-System Programmable Configuration PROMs Pinout and Pin Description Table 1 provides a list of the pin names and descriptions for the 44-pin VQFP and PLCC and the 20-pin SOIC and PLCC packages. Table 1: Pin Names and Descriptions ...
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R Table 1: Pin Names and Descriptions (Continued) Boundary Pin Scan Name Order Function CF 22 DATA OUT 21 OUTPUT ENABLE CEO 12 DATA OUT 11 OUTPUT ENABLE GND TMS MODE SELECT TCK CLOCK TDI DATA IN TDO DATA OUT ...
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XC18V00 Series In-System Programmable Configuration PROMs Pinout Diagrams TDI TMS 11 PC44 12 GND Top View TCK CCO TDI 3 ...
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R Xilinx FPGAs and Compatible PROMs Table 2 provides a list of Xilinx FPGAs and compatible PROMs. Table 2: Xilinx FPGAs and Compatible PROMs Configuration Device Bits XC2VP2 1,305,440 XC2VP4 3,006,560 XC2VP7 4,485,472 XC2VP20 8,214,624 XC2VP30 11,364,608 XC2VP40 15,563,264 XC2VP50 ...
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XC18V00 Series In-System Programmable Configuration PROMs Table 2: Xilinx FPGAs and Compatible PROMs Configuration Device Bits XC3S1500 5,214,784 XC3S2000 7,673,024 XC3S4000 11,316,864 XC3S5000 13,271,936 Capacity Devices Configuration Bits XC18V04 XC18V02 XC18V01 XC18V512 In-System Programming In-System Programmable PROMs can be programmed ...
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R The read security bit can be set by the user to prevent the internal programming pattern from being read or copied via JTAG. When set, it allows device erase. Erasing the entire device is the only way to reset ...
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XC18V00 Series In-System Programmable Configuration PROMs Table 5 lists the IDCODE register values for the XC18V00 devices. Table 5: IDCODES Assigned to XC18V00 Devices ISP-PROM IDCODE XC18V01 05024093h or 05034093h XC18V02 05025093h or 05035093h XC18V04 05026093h or 05036093h XC18V512 05023093h ...
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R Connecting Configuration PROMs Connecting the FPGA device with the configuration PROM (see Figure 5 and Figure 6). • The DATA output(s) of the PROM(s) drives the D input of the lead FPGA device. • The Master FPGA CCLK output ...
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XC18V00 Series In-System Programmable Configuration PROMs VCCO VCCINT (See Note 2) VCCINT VCCO XC18V00 Cascaded PROM J1 1 TDI TDI 2 TMS TMS 3 TCK TCK 4 TDO OE/RESET GND Notes: 1 For Mode pin connections and DONE pin pullup ...
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R DOUT FPGA Vcco (1) Modes DIN CCLK DONE INIT PROGRAM Notes: 1 For Mode pin connections and Done pullup value, refer to the appropriate FPGA data sheet. 2 For compatible voltages, refer to the appropriate FPGA data sheet. (a) ...
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XC18V00 Series In-System Programmable Configuration PROMs Reset Activation On power up, OE/RESET is held low until the XC18V00 is active (1 ms). OE/RESET is connected to an external 4.7kΩ resistor to pull OE/RESET HIGH releasing the FPGA INIT and allowing ...
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R Absolute Maximum Ratings Symbol V V Supply voltage relative to GND CCINT/ CCO V Input voltage with respect to GND IN V Voltage applied to High-Z output TS T Storage temperature (ambient) STG T Maximum soldering temperature (10s @ ...
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XC18V00 Series In-System Programmable Configuration PROMs DC Characteristics Over Operating Conditions Symbol Parameter V High-level output voltage for 3.3V outputs OH High-level output voltage for 2.5V outputs V Low-level output voltage for 3.3V outputs OL Low-level output voltage for 2.5V ...
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R AC Characteristics Over Operating Conditions for XC18V04 and XC18V02 CE OE/RESET CLK T CE DATA Symbol T OE/RESET to data delay data delay CE T CLK to data delay CAC T Data hold from CE, ...
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XC18V00 Series In-System Programmable Configuration PROMs AC Characteristics Over Operating Conditions for XC18V01 and XC18V512 CE OE/RESET CLK T CE DATA Symbol T OE/RESET to data delay data delay CE T CLK to data delay CAC ...
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R AC Characteristics Over Operating Conditions When Cascading for XC18V04 and XC18V02 OE/RESET CE CLK DATA CEO Symbol T CLK to data float delay CDF (3) T CLK to CEO delay OCK ( CEO delay OCE T ...
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XC18V00 Series In-System Programmable Configuration PROMs AC Characteristics Over Operating Conditions When Cascading for XC18V01 and XC18V512 OE/RESET CE CLK DATA CEO Symbol T CLK to data float delay CDF (3) T CLK to CEO delay OCK ( ...
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R Ordering Information Device Number XC18V04 Package Type XC18V02 VQ44 = 44-pin Plastic Quad Flat Package XC18V01 PC44 = 44-pin Plastic Chip Carrier XC18V512 SO20 = 20-pin Small-Outline Package PC20 = 20-pin Plastic Leaded Chip Carrier Notes: 1. XC18V04 and ...
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XC18V00 Series In-System Programmable Configuration PROMs Revision History The following table shows the revision history for this document. Date Version 2/9/99 1.0 First publication of this early access specification 8/23/99 1.1 Edited text, changed marking, added CF and parallel load ...
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R 04/17/03 3.10 Changes to Description, 06/11/03 4.0 Added alternate industrial ordering combinations, extended commercial temperature range, and added MultiPRO Desktop Tool support. Changed T page 15 Operating 12/15/03 4.1 • • DS026 (v4.1) December 15, 2003 Product Specification XC18V00 ...