PLC810PG Power Integrations, PLC810PG Datasheet
PLC810PG
Specifications of PLC810PG
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PLC810PG Summary of contents
Page 1
... The highside/lowside duty cycle is also closely matched to provide balanced output currents reducing output diode cost. A typical PLC810PG LLC design operates at 100 kHz (under nominal conditions). Depending on the LLC circuit design, the switching frequency can vary from half to three times the nominal operating frequency as a result of line and load changes ...
Page 2
... PLC810PG becomes discontinuous improving light load operation and reducing power line harmonics. PFC and LLC primary side fault management is provided. The phase of the PFC PWM output is dynamically adjusted relative to the LLC phase such that the switching edges do not coincide with noise sensitive events in the PWM and LLC timing circuits ...
Page 3
... HB Half-bridge pin. This pin is the return of the LLC high side MOSFET driver. It must be connected to the center of the half- www.powerint.com PLC810PG bridge formed by the LLC MOSFETs. The VCCHB bypass capacitor must also be returned to this pin. ISP Current sense, PFC for sensing the negative voltage on the current sense resistor (which describes PFC inductor current) ...
Page 4
... PLC810PG FMAX This pin is for programming maximum LLC frequency with a resistor to VREF. If the frequency commanded by the FBL pin current exceeds 95% of the programmed maximum frequency, the LLC high and low side drivers turn both LLC MOSFETs off. This pin must be decoupled to the GND pin with capacitor ...
Page 5
... The VCCL pin powers the LLC driver, and VCCHB provides the charge for the LLC high-side MOSFET for gate drive. An internal linear regulator is used to generate a 3.3 V rail to power the low voltage circuits inside the PLC810PG. The 3 brought outside on the VREF pin allowing external low voltage circuits to be powered by the PLC810PG. ...
Page 6
... changes slowly with the input voltage, the average OFF current will be in-phase with the input voltage. The PLC810PG PFC block controls the PFC off-time (D The output voltage needs to be regulated and R adjusted as a function of the load and the input voltage. The PLC810PG PFC has two inputs: The feed-back PFC output voltage is reduced by a resistor • ...
Page 7
... The dead time block is used both by the PFC and LLC to control the dead time of the switching function. The dead time in the PLC810PG is configurable via the FMAX pin. The dead time allows zero voltage switching, reducing the body diode losses in the ...
Page 8
... PLC810PG Figure 4. PLC810PG LCD TV Power Supply Application Circuit, PFC Circuit Control Inputs and LLC Stage. 8 Rev. F 08/09 www.powerint.com ...
Page 9
... C3 330 pF 470 pF 250 VAC 275 VAC TP3 N Bridge + V CC GATEP Controller GND ISP Bridge - Figure 5. PLC810PG LCD TV Power Supply Application Circuit, Input Circuit and PFC Power Stage. B+ C13 20 nF 500 V TP28 U1B Remote LTV817A On/Off R15 Q4 330 kΩ BST52TA R14 kΩ ...
Page 10
... Circuit Description Figures 4, 5, and 6 show the schematic of a typical 280 W LCD TV power supply application using HiperPLC and TinySwitch-III. The PSU contains PFC + LLC stage using a PLC810PG which provides the high power outputs, plus a standby power supply using a TNY275PN. The design has 4 outputs and main and 5 V standby ...
Page 11
... LLC stages. PFC Control The PFC boost stage output voltage is fed back to the FBP pin of the PLC810PG via resistors R39-41, R43, R46, and R50 capacitor (C25) filters noise. Capacitor C26, C28 and R48 provide frequency compensation for the PFC. The PFC current sense signal from resistors R6 and R8 is filtered by R45 and C24 ...
Page 12
... LLC Controller Section The LLC converter is a variable frequency converter (an LLC converter’s output power decreases as frequency increases). The designer needs to set the minimum and maximum frequencies of the PLC810PG to suit the power train. 12 Rev. F 08/09 FMAX Pin The FMAX pin is connected via a programming resistor to the VREF pin ...
Page 13
... We can and then substitute this into (1) and rearrange Where V FBL CESAT diode forward voltage drop 3.25 V (nominal) REF START PLC810PG (the initial frequency at start-up the frequency that the LLC MIN MIN is determined by the MIN in Figure 16. Set R4 according to the equation FBL(max) (FBL pin current) and frequency is FBL ...
Page 14
... LLC MOSFET half-bridge output. These are HB, VCCHB, and GATEH (pins 12, 13, and 14). These pins must be isolated from the rest of the pins on the PLC810PG (extra package isolation is also provided by omitting pins 11 and 15). Because these pins have high dv/dt, the traces and components connected to them have to be kept away from low voltage pins ...
Page 15
... GND trace between the GATEP and ISP signal traces. This will reduce potential noise coupling from the GATEP trace to the ISP trace. See Figure 12. FBL Pin Circuitry and Optocoupler See Figure 13. The FBL pin circuitry should be mounted close to the PLC810PG. The feedback optocoupler is typically Isolation Spacing PI-5283-111008 15 ...
Page 16
... The gate resistor (R28) should also be mounted close to the MOSFET. HB and GATEH Refer to Figure 11. The HB and GATEH lines should run side by side from the LLC high side MOSFET to the PLC810PG. The gate resistor (R26) should be mounted close to the MOSFET. 16 Rev. F 08/09 ...
Page 17
... Figure 12. PFC Power and Signal Layout Recommendations. GATEP Figure 13. PFC Gate Drive Circuit Recommendation. www.powerint.com Dedicated GND trace to sense R Dedicated ISP trace to sense R ISP, GND, GATEP traces side-by-side 12 V Standby R4 10 Ω Q8 FMMT491 R33 10 Ω C28 1 µ FMMT591 R107 4.7 kΩ PI-5278-111108 PLC810PG PI-5282-111008 Q7 SPA21N50C3 17 Rev. F 08/09 ...
Page 18
... Table 1. Absolute Maximum Ratings. DC operating characteristics Table 2 lists the minimum, typical, and maximum DC operating voltages and currents for all inputs and outputs of PLC810PG. Negative currents flow out of the IC, positive currents flow into the IC. The DC operating characteristics are for a junction Parameter Symbol ...
Page 19
... REF FBL soft start reset (4096 F cycles MAX instantaneous) ISL ISL 8 Cycle de-bounce Minimum time VISL exceeds ISL V /V per cycle to ISL(F) ISL(S) trigger fault PLC810PG Min Typ Max 8.2 9.1 10 9.2 7.2 8.1 9.0 8.7 0.7 1.0 1.3 50 300 -15 ...
Page 20
... PLC810PG Parameter Symbol PFC PFC Overcurrent V Limit Threshold OC PFC Output Continuous DC Duty Cycle Range PFC PFC Error Amplifier V Reference FBPREF PFC Error Amplifier FBPREF Reference Accuracy PFC Overvoltage V Threshold OV(H) PFC Inhibit INH Upper Threshold PFC Inhibit INL Lower Threshold Transconductance ...
Page 21
... GATEL I = 130 mA OL GATEH/ VCCL/VCCHB = 12 V GATEL PW <10 mS GATEH/ VCCL/VCCHB = <10 mS GATEL HB GATEH, VCCL/VCCHB = 12 V GATEL 1000 pF load capacitance GATEH, VCCL/VCCHB = 12 V GATEL 1000 pF load capacitance PLC810PG Min Typ Max Units VHB VCCHB VCOM VCCL 11 11 -0.8 -0.5 A 0.9 1.4 A ...
Page 22
... PLC810PG Typical Performance Characteristics 200 250 300 350 400 450 500 550 Dead-Time (ns) Figure 14. FMAX Pin Pull-up Resistor to VREF Pin vs. Dead-time Requirement. 100 Frequency (kHz) Figure 16. Pull-up Resistance from FBL Pin to VREF Pin vs. Switching Frequency 22 Rev. F 08/09 300 280 260 240 ...
Page 23
... Package Information and Part Marking The PLC810PG is packaged lead 0.300 PDIP package (Figure 18 shows the PLC810PG part marking). Figure 19 shows the package outline and dimensions Power Integrations Registered Trademark B. Encapsulation Date Code (last two digits of year followed by 2-digit work week) C. Product Identification (Part #/Package Type) D ...
Page 24
... PLC810PG 24 1 0.015 (0.38) MIN 0.015 (0.38) 0.100 (2.54) 0.020 (0.51) Figure 19. PDIP-24 Package Marking. 24 Rev. F 08/09 PDIP-24 (0.300”) 13 0.240 (6.10) 0.270 (6.86) 12 1.240 (31.50) 1.260 (32.00) 0.055 (1.40) 0.065 (1.65) 0.010 (0.25 Notes: 1. Package dimensions conform to JEDEC specification MS-001. ...
Page 25
... Revision Notes A Initial Release B Revised figures and text C Text, schematic updates D Schematic updates E Fixed schematic Figure 4 error and removed Note 2 from Parameter Table F Updated Figures and 18 www.powerint.com PLC810PG Date 11/08 11/08 12/08 02/09 05/09 08/09 25 Rev. F 08/09 ...
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... The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S. and foreign patents, or Power Integrationslly by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a license under certain patent rights as set forth at http://www ...