NCP1294EDBR2G ON Semiconductor, NCP1294EDBR2G Datasheet
NCP1294EDBR2G
Specifications of NCP1294EDBR2G
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NCP1294EDBR2G Summary of contents
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... WW Work Week Pb−Free Package ORDERING INFORMATION Device Package NCP1294EDR2G SOIC−16 (Pb−Free) NCP1294EDBR2G TSSOP−16 (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 1 SOIC−16 D SUFFIX CASE 751B TSSOP− ...
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NCP1294 Figure 1. Application Diagram, 36 V− 5.0 V/5.0 A Converter http://onsemi.com 2 ...
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MAXIMUM RATINGS Operating Junction Temperature Lead Temperature Soldering: Storage Temperature Range ESD (Human Body Model) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions ...
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ELECTRICAL CHARACTERISTICS (−40°C < 390 pF; unless otherwise specified Characteristic Reference Voltage Total Accuracy Line Regulation Load Regulation Noise Voltage Op Life Shift Fault Voltage V Voltage REF(OK) V Hysteresis REF(OK) ...
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ELECTRICAL CHARACTERISTICS (−40°C < 390 pF; unless otherwise specified Characteristic Gate Driver High Saturation Voltage Low Saturation Voltage High Voltage Clamp Output Current Output UVL Leakage Rise Time Fall Time Max ...
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PACKAGE PIN DESCRIPTION Package Pin Pin # Symbol 1 GATE External power switch driver with 1.0 A peak capability. Rail to rail output occurs when the capacitive load is between 470 pF and 10 nF Current sense comparator ...
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UVL − ENABLE + − UV Lockout Start/Stop SYNC 2 1.0 V Trip Points V 3 (1.263 V) − EAMP − COMP Soft−Start Clamp FF ...
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THEORY OF OPERATION Feed Forward Voltage Mode Control In conventional voltage mode control, the ramp signal has fixed rising and falling slope. The feedback signal is derived solely from the output voltage. Consequently, voltage mode control has inferior line regulation ...
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Soft−Start can be programmed through a capacitance connected to the SS pin. The constant charging current to the SS pin (typ). The V (ok) comparator monitors the 3 REF output and latches a ...
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Figure 8. The SYNC Pin Generates a Sync Pulse at the Beginning of Each Switching Cycle. CH2: GATE Pin, CH3 CH4: SYNC Pin T T Figure 9. Operation with External Sync. CH2: SYNC Pin, CH3: GATE Pin, ...
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500 400 300 200 100 0.0001 0.001 C (mF) T Figure 10. Typical Performance Characteristics, Oscillator Frequency vs. C that during ...
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G K −T− SEATING PLANE 0.25 (0.010 PACKAGE THERMAL DATA Parameter R qJC R qJA PACKAGE DIMENSIONS SOIC−16 D SUFFIX CASE 751B−05 ISSUE K −B− 0.25 ...
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... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...