NCP1294EDBR2G ON Semiconductor, NCP1294EDBR2G Datasheet - Page 10

• Manufacturer Part Number: NCP1294EDBR2G
• Description: IC PWM CTLR FLYBACK 16TSSOP
• Manufacturer: ON Semiconductor

Specifications of NCP1294EDBR2G

• Output Isolation: Isolated
• Frequency Range: 260 ~ 320kHz
• Voltage - Input: 4.7 ~ 15 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-TSSOP
• Duty Cycle (max): 90 %
• Output Current: 1 A
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.05 V
• Supply Current: 9.5 mA
• Fall Time: 25 ns
• Rise Time: 60 ns
• Synchronous Pin: Yes
• Topology: Boost, Flyback, Forward
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SYNC pin to synchronize the switch frequency. For reliable
operation, the sync frequency should be approximately 20%
higher than free running IC frequency. As show in Figure 9,
when the SYNC pin is triggered by an incoming signal, the
IC immediately discharges C
on once the R
the steep falling edge, this valley voltage falls below the
regular 1.0 V threshold. However, the R
then quickly raised by a clamp. When the R
the 0.95 V (typ) Valley Clamp Voltage, the clamp is
disconnected after a brief delay and C
R
T
An external pulse signal can feed to the bidirectional
.
Figure 8. The SYNC Pin Generates a Sync Pulse at
CH2: SYNC Pin, CH3: GATE Pin, CH4: R
CH2: GATE Pin, CH3: R
the Beginning of Each Switching Cycle.
Figure 9. Operation with External Sync.
T
C
T
pin reaches the valley voltage. Because of
T
. The GATE signal is turned
T
C
T
, CH4: SYNC Pin
T
is charged through
T
C
T
T
C
pin voltage is
T
T
pin reaches
C
T
Pin
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10
Switch Frequency and Maximum Duty Cycle
Calculations
through R
During the discharge time, the internal clock signal sets the
Gate output to the low state, thus providing a user selectable
maximum duty cycle clamp. Charge and discharge times are
determined by following general formulas;
where:
above formulas, V
2.0 V, I
function properly, R
Select RC for Feed Forward Ramp
Voltage, the charge current can be treated as a constant and
is equal to V
determined by:
where:
the V
Forward or Flyback circuits, the volt−second clamp value is
designed to prevent transformers from saturation.
n = transformer turns ratio, which is a constant determined
by the regulated output voltage, switching period and
transformer turns ration (use 1.0 for buck converter). It is
interesting to notice from the aforementioned two equations
Oscillator timing capacitor, C
Substituting in typical values for the parameters in the
It is noticed from the equation that for the oscillator to
If the line voltage is much greater than the FF pin Peak
V
V
As shown in the equation, the volt−second clamp is set by
In a buck or forward converter, volt−second is equal to
V
V
t
t
COMP
FF(d)
C
d
VALLEY
PEAK
= discharging time;
= charging time;
COMP
t d + R T C T ln
V IN
d
= 1.0 mA:
= FF pin discharge voltage.
T
= COMP pin voltage;
t C + R T C T ln
= peak voltage of the oscillator.
and discharged by an internal current source.
clamp voltage which is equal to 1.8 V. In
= valley voltage of the oscillator;
T ON + (V COMP * V FF(d) )
t d + R T C T ln
D max +
V IN
IN
DESIGN GUIDELINES
/R. Therefore, the volt−second value is
REF
T
t C + 0.57R T C T
T ON +
(V REF * V VALLEY * I d R T )
has to be greater than 2.3 k.
(V REF * V PEAK * I d R T )
= 3.3 V, V
0.57 ) In
(V REF * V VALLEY )
(V REF * V PEAK )
1.3 * 0.001R T
2.3 * 0.001R T
V OUT
0.57
VALLEY
T
1.3*0.001R T
2.3*0.001R T
, is charged by V
n
T S
= 1.0 V, V
R
C
PEAK
REF
=